Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric

Analysis of electron mobility in HfO2/TiN gate metal-oxide-semiconductor field effect transistors: The influence of HfO2 thickness, temperature, and oxide charge

“…Hafnium-based high-k dielectrics and metal gate electrodes have been extensively investigated as alternative gate materials, [1][2][3][4][5][6][7][8][9][10][11] and the successful incorporation of hafnium based high-k materials into the gate stack of MOSFETs with minimum feature sizes of 45 nm has recently been announced. 12 However, there are still many issues associated with the implementation of these materials.…”

“…[1][2][3][4][5][6][7][8][9][10][11] This degradation has been attributed to the contributions of oxide charge in the high-k layer ͑columbic scattering͒, high-k phonon scattering, silicon phonon scattering, and surface roughness scattering. It has recently been demonstrated that interface defect densities in the range of ͑3-4͒ ϫ 10 10 cm −2 and fixed positive oxide charge densities Ͻ2 ϫ 10 12 cm −2 do not yield significant mobility degradation.…”

“…9,11 The temperature dependence of the electron mobility from 50 to 350 K is determined before and after the various levels of oxide and interface degradations. This new approach provides an experimental route for the determination of the Coulomb scattering term as a function of temperature for various oxide charge levels.…”

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

“…However, as the gate dielectric is thinned, the amplitude of the semiconductor surface asperities at the dielectric interface becomes a larger proportion of the total dielectric thickness hence 2 nd order effects become non-negligible. The model in equation 3 was shown to account more accurately for mobility degradation in thin gate dielectric MOSFETs and has been used in other studies [16][17][18]. In this paper, the linearity of strained Si nMOSFETs is assessed, the 2 nd order MDF (θ 2 ) is extracted for 2.5 nm thick oxides and a MOSFET model is used to assess the importance of θ 2 in the predictive modelling of linearity for CMOS devices.…”

Charge trapping in MOSFETs with HfSiON dielectrics during electrical stressing

“…In the scaling of MOSFETS, the gate dielectric plays a critical role, and an extensive range of papers exist on the subject of estimating the lifetime and integrity of these layers as they become thinner and are subjected to ever increasing current densities and electric fields [1][2][3].…”