Analysis of electron mobility in HfO2/TiN gate metal-oxide-semiconductor field effect transistors: The influence of HfO2 thickness, temperature, and oxide charge

Abstract

We report a new analysis of electron mobility in HfO 2 / TiN gate metal-oxide-semiconductor field effect transistors ͑MOSFETs͒ by investigating the influence of HfO 2 thickness ͑1.6-3 nm͒, temperature ͑50-350 K͒, and oxide charge ͑ϳ1 ϫ 10 11 -8ϫ 10 12 cm −2 ͒ in the high inversion charge region. The fixed oxide charge and interface state densities are deliberately increased using negative-bias-temperature stress, allowing the determination of the Coulomb scattering term as a function of temperature for various oxide charge levels. The temperature dependence of the Coulomb scattering term is consistent with the case of a strongly screened Coulomb potential. Using the experimentally determined temperature dependence of Coulomb scattering term, a model is developed for the electron mobility, including the effects oxide charge ͑ C ͒, high-k phonon ͑ Ph-Hk ͒, silicon phonon ͑ Ph-Si ͒, and surface roughness scattering ͑ SR ͒. The model provides an accurate description of the experimental data for variations in HfO 2 thickness, temperature, and oxide charge. Using the model the relative contributions of each mobility component are presented for varying oxide charge and high-k thickness. Scaling of the HfO 2 physical thickness provided a reduction in the oxide charge and high-k phonon scattering mechanisms, leading to an increase in electron mobility in HfO 2 / TiN gate MOSFETs.

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

“…In the linear regime, the FTCE can significantly impact mobility [31,63,64,66,79,83,91,92,[96][97][98]. In a conventional DC sweep of the I d -V g measurement, the threshold voltage shifts as the measurement progresses, thereby decreasing the drive current at each bias sweep point resulting in decreased mobility.…”

Investigation of nonuniformity phenomenon in nanoscale SiO2 and high-k gate dielectrics

“…It has been reported that the oxide trap charges would be reduced by the scaling of the HfO 2 thickness. 4,5 It is believed that the thicker high-k oxides will contain more oxide trap charges and defects during the formation of the high-k gate dielectrics. This phenomenon is general and fundamental for the high-k gate dielectrics due to the inherent imperfect dielectric interface.…”

“…1,2 Meanwhile, to maintain the physical thickness of gate oxide, HfO 2 has been considered as one of the most promising high-k materials to replace the conventional SiO 2 due to its high dielectric constant and good thermodynamics stability. [3][4][5] On the other hand, in order to test the ultrathin dielectric characteristics for MOS or non-volatile memory devices, large-area MOS capacitors (MOSCAPs) are still commonly used. The capacitance-voltage (C-V) measurement is an important technique to investigate the electrical characteristics of MOS devices.…”

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

“…However, the commonly observed severe mobility degradation from thinning down the SiO x interface layer (IL) [5] reduces the EOTscaling benefits. While there are results elaborating on the origin of the low mobility [3,6], little has been done on UTEOT devices with alternative channels. In this paper, the mobility at UTEOT is compared for bulk Si, ultrathin-body SOI (FDSOI) with ultrathin BOX (UTBOX) [7], and SiGe quantum well devices.…”