Capacitors with an Equivalent Oxide Thickness of <0.5 nm for Nanoscale Electronic Semiconductor Memory

Abstract

The recent progress in the metal‐insulator‐metal (MIM) capacitor technology is reviewed in terms of the materials and processes mostly for dynamic random access memory (DRAM) applications. As TiN/ZrO2‐Al2O3‐ZrO2/TiN (ZAZ) type DRAM capacitors approach their technical limits, there has been renewed interest in the perovskite SrTiO3, which has a dielectric constant of >100, even at a thickness ∼10 nm. However, there are many technical challenges to overcome before this type of MIM capacitor can be used in mass‐production compatible processes despite the large advancements in atomic layer deposition (ALD) technology over the past decade. In the mean time, rutile structure TiO2 and Al‐doped TiO2 films might find space to fill the gap between ZAZ and SrTiO3 MIM capacitors due to their exceptionally high dielectric constant among binary oxides. Achieving a uniform and dense rutile structure is the key technology for the TiO2‐based dielectrics, which depends on having a dense, uniform and smooth RuO2 layer as bottom electrode. Although the Ru (and RuO2) layers grown by ALD using metal‐organic precursors are promising, recent technological breakthroughs using the RuO4 precursor made a thin, uniform, and denser Ru and RuO2 layer on a TiN electrode. A minimum equivalent oxide thickness as small as 0.45 nm with a low enough leakage current was confirmed, even in laboratory scale experiments. The bulk dielectric constant of ALD SrTiO3 films, grown at 370 °C, was ∼150 even with thicknesses ≤15 nm. The recent development of novel group II precursors made it possible to increase the growth rate largely while leaving the electrical properties of the ALD SrTiO3 film intact. This is an important advancement toward the commercial applications of these MIM capacitors to DRAM as well as to other fields, where an extremely high capacitor density and three‐dimensional structures are necessary.

Smooth, Low-Resistance, Pinhole-Free, Conformal Ruthenium Films by Pulsed Chemical Vapor Deposition

“…1 During the annealing process, agglomeration could roughen the surface of the films. Therefore, we also measured the surface roughness of a Ru/WN film before and after rapid thermal annealing (RTA).…”

“…One of the most important potential applications is as an electrode material in DRAM structures, where Ru will be deposited inside hole structures. 1 In order to obtain high conformality of deposition, lower deposition temperature and higher precursor vapor pressure are 7 usually needed. 21 Therefore, we examined the temperature dependence of the deposition rate as shown in Figure 6.…”

Medium energy ion scattering for the high depth resolution characterisation of high-k dielectric layers of nanometer thickness

“…Hence the problem with the N profile seen above is not a generic problem. The final example is a layer structure largely identical to the previous sample but for the fact that the TiO 2 is doped with 1% Al for the purpose of reducing the leakage current density of the MIMCAP stacks [41]. The layer structure was annealed in Ar for 60 s at 370 °C and the issue of interest was the fate of the Al dopant upon annealing.…”

Si:SrTiO3-Al2O3-Si:SrTiO3 multi-dielectric architecture for metal-insulator-metal capacitor applications

“…7 SrTiO 3 (STO) has been the most studied perovskite dielectric, offering high dielectric constant >100 (ultra high-k) even in the form of ultra-thin layers. 8 Along with a low bandgap of 3.2 eV, it has a paraelectric phase above 105 K. 9,10 However, crystalline layers of STO suffer from high leakage current densities originating from the grain boundary channel as well as a decreased metal/insulator barrier height due to its inherent low bandgap. These problems can be solved by using an STO layer in its amorphous phase and by stacking it with large-bandgap materials (e. g., Al 2 O 3 , SiO 2 , MgO etc.)…”