Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

Chen, Yen‐Ting; Sun, Haiyan; Huang, Chih‐Fen; Wu, Ting-Yun; C, Liu; Hsu, Yuan‐Jun; Chen, Jim‐Shone

doi:10.1109/led.2010.2057406

Cited by 8 publications

(7 citation statements)

References 11 publications

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“…In recent years, poly-Si 1T-DRAM has gained much attention [15][16][17][18][19][20]. This type of device stores its charge in its grain boundary (GB) instead of in the FB, and therefore it is advantageous for short channel devices; its charge can be stored in the GB even with a thin body.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

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Section: Introductionmentioning

confidence: 99%

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

et al. 2020

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“…Therefore, capacitorless one-transistor dynamic random-access memory device (1T-DRAM), which does not need capacitor fabrication, has emerged as an alternative to conventional 1T-1C-DRAM [ 1 , 2 , 3 , 4 , 5 ]. In recent years, among the various types of 1T-DRAM, poly-Si 1T-DRAM is being researched actively [ 5 , 6 , 7 , 8 , 9 , 10 , 11 ]. Poly-Si 1T-DRAM exhibits small degradation over short channels because it can operate as memory in fully depleted silicon-on-insulator (FD-SOI) structures using grain boundary (GB) [ 10 , 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, among the various types of 1T-DRAM, poly-Si 1T-DRAM is being researched actively [ 5 , 6 , 7 , 8 , 9 , 10 , 11 ]. Poly-Si 1T-DRAM exhibits small degradation over short channels because it can operate as memory in fully depleted silicon-on-insulator (FD-SOI) structures using grain boundary (GB) [ 10 , 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

“…Studies on poly-Si 1T-DRAM devices have focused on overcoming the limitations of conventional silicon 1T-DRAM devices and improving memory performance, and therefore, the focus has been on device-level simulation [ 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 ]. Although it is important for a single 1T-DRAM device to have adequate performance as memory, a single device cannot be used as memory.…”

Section: Introductionmentioning

confidence: 99%

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Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

Shin

Sun

et al. 2021

Micromachines

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A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level operation to replace 1T-1C-DRAM. To utilize 1T-DRAM as a memory device, we must understand its circuit-level operation, in addition to its device-level operation. Therefore, we studied the memory performance depending on device location in an array circuit and the circuit configuration by using the 1T-DRAM structure reported in the literature. The simulation results show various disturbances and their effects on memory performance. These disturbances occurred because the voltages applied to each device during circuit operation are different. We analyzed the voltage that should be applied to each voltage line in the circuit to minimize device disturbance and determine the optimized bias condition and circuit structure to achieve a large sensing margin and realize operation as a memory device. The results indicate that the memory performance improves when the circuit has a source line and the bias conditions of the devices differ depending on the write data at the selected device cell. Therefore, the sensing margin of the 1T-DRAM used herein can expectedly be improved by applying the proposed source line (SL) structure.

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“…In recent years, 1T-DRAM devices with poly-Si bodies have been studied to overcome the limitations of silicon 1T-DRAM [ 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ]. Since the poly-Si devices use grain boundaries (GBs) instead of a FB as a charge storage region, they can perform memory operations in a FD-SOI structure [ 15 ].…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

2020

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A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.

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Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries

Cited by 8 publications

References 11 publications

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

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