Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM

Abstract

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM

“…In our previous study, we proposed a method of optimizing the body thickness and bias conditions to simultaneously consider the memory performance and the short channel effects (SCEs) of a short-channel poly-Si 1T-DRAM cell [18]; we confirmed that thick body devices with a larger GB area have better memory performance than thin body devices because they have a larger amount of trapped charge. Also, in other studies, we verified that the sensing margin and retention time of a poly-Si 1T-DRAM cell are significantly affected by the number and location of the vertical GBs randomly determined during fabrication [15,17]. The memory performance of a poly-Si device in which a single GB is located near the source and drain is significantly reduced; the device's sensing margin is inversely proportional to the number of GBs in its body.…”

“…The inset in Figure 2 a shows trap densities according to band energy. We set the simulation trap parameter based on recent studies [ 15 , 16 , 17 , 18 ]. In the recent research of Reference [ 16 ], the investigators verified that the transient drain current is a function of the trap densities; donor type traps have little influence on the drain current while acceptor type trap densities are inversely proportional to the drain current.…”

“…Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells are severely limited in integration density because it is difficult to miniaturize their capacitors, so capacitorless 1T-DRAM has attracted attention as a promising alternative [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 ]. 1T-DRAM devices composed of one silicon-on-insulator (SOI) transistor have different operating mechanisms depending on their body material [ 15 ]. A 1T-DRAM device with a silicon body differentiates its state using current differences in the number of holes stored in its floating body (FB).…”

“…Although a silicon body 1T-DRAM device can have a small cell size of 4F 2 , it cannot operate as a memory in a fully depleted-SOI (FD-SOI) structure that lacks a FB hole storage region. This means that short channel silicon 1T-DRAM devices with small depletion regions have significantly deteriorated memory performance [ 15 ].…”

“…In recent years, 1T-DRAM devices with poly-Si bodies have been studied to overcome the limitations of silicon 1T-DRAM [ 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ]. Since the poly-Si devices use grain boundaries (GBs) instead of a FB as a charge storage region, they can perform memory operations in a FD-SOI structure [ 15 ]. Polysilicon has GBs due to its multiple single-crystalline silicon composition; a poly-Si 1T-DRAM device distinguishes its data by using the charge trapping characteristic of GBs.…”