Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.
Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application.
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory’s operating mechanism changes with the GB’s lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.
A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.
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