Capacitance Transient Spectroscopy Measurements on High-k Metal Gate Field Effect Transistors Fabricated Using 28nm Technology Node

Abstract

Fast progress in nanometer-node high-k metal gate (HKMG) technology requires the development of versatile and detailed characterization methods for semiconductor / dielectric / metal stacks and interfaces between them. Complexity of the advanced fabrication processes does not allow preparation of model samples with dimensions used in standard laboratory measurements. In this report we apply capacitance transient spectroscopy measurements for the characterization of HKMG field effect transistors (FET) fabricated in the standard 28 nm node technology. Measurements were performed on n-FET devices. The devices were characterized in the as-fabricated stage, after application of electrical stress and after fluorine implantation introduced to passivate the interface carrier traps. Our results show good correspondence with those obtained by other characterization methods and supply detailed information on the energy distribution of the interface trap density in the system.

Interface traps in 28 nm node field effect transistors detected by capacitance transient spectroscopy

“…The total sampling time for transients was 0.012 s, measurement parameters: U B = 0.15 V, U P 1 = −1.5 V, U P 2 = −0.5 V (see Ref. for details). Labeling of data is given in the figure and explained in Table .…”

“…After complete CMOS processing the device structures were cut out of the wafers and bonded into chip‐housings (see Ref. ). Similar structures without housings were also investigated.…”

“…The gate (G) contact and the source/drain/bulk (S/D/B) contact were connected to the tips by thin golden wires in the case of samples with housing, like it was presented in Ref. . For unhoused structures the DUT pads were directly contacted by the tips.…”

“…The procedure of obtaining the energy distribution of the interface trap density from the detected transients, together with the measurement sequence and experimental details, were presented in the previous report . The only difference in the measurement process for the samples without housing was that due to the thermal expansion of the system components it was necessary to disconnect the tips from the pads during every cooling/heating sequence and reconnect them after temperature stabilization.…”

“…In our previous report , we presented first results of CTS measurements on HKMG FET structures fabricated under production conditions, with real dimensions of the working elements and after application of the full cycle of production processes, including packaging. The results clearly showed the influence of Fluorine passivation and the effect of electrical stresses on the trap density and trap energy distribution in the dielectric layers . In the present work, we report on further investigations of FET devices fabricated under various conditions and on comparison of the results obtained by CTS with those obtained by common characterization technique.…”