Can trace-driven simulators accurately predict superscalar performance?

Black, Bryan; Huang, Andrew S.; Lipasti, Mikko H.; Shen, John Paul

doi:10.1109/iccd.1996.563596

Cited by 25 publications

(12 citation statements)

References 11 publications

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“…Our work is a positive response to the question "Can trace-driven simulators accurately predict superscalar performance?" posed by Black et al [4]. In their work in 1996, they determined that sampling techniques present a problem to the accuracy of trace-driven simulation for superscalar processors, and questioned the accuracy of trace-driven simulation for superscalar processors even when the full traces were used as the processor complexity continues to increase and the benchmarks evolve to run for longer times.…”

Section: Related Workmentioning

confidence: 98%

Accurately approximating superscalar processor performance from traces

Lee

Evans

Cho

2009

2009 IEEE International Symposium on Performance Analysis of Systems and Software

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Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to large inaccuracies in the results, especially when traces contain only a subset of executed instructions for trace reduction. The main problem in the filtered trace simulation is that the trace does not contain enough information with which one can predict the actual penalty of a cache miss. In this paper, we discuss and evaluate three strategies to quantify the impact of a long latency memory access in a superscalar processor when traces have only L1 cache misses. The strategies are based on models about how a cache miss is treated with respect to other cache misses: (1) isolated cache miss model, (2) independent cache miss model, and(3) pairwise dependent cache miss model. Our experimental results demonstrate that the pairwise dependent cache miss model produces reasonably accurate results (4.8% RMS error) under perfect branch prediction. Our work forms a basis for fast, accurate, and configurable multicore processor simulation using a pre-determined processor core design.

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Section: Related Workmentioning

confidence: 98%

Accurately approximating superscalar processor performance from traces

Lee

Evans

Cho

2009

2009 IEEE International Symposium on Performance Analysis of Systems and Software

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“…Black et al [28] investigate the number of retired instructions and cycles on the PowerPC 604 platform, comparing their results against a cycle-accurate simulator. Cycle-accurate simulators have their own inherent error, so unless that is known exactly it limits what can be learned about the accuracy of the hardware counters being compared.…”

Section: Related Workmentioning

confidence: 99%

Non-determinism and overcount on modern hardware performance counter implementations

Weaver

Terpstra

Moore

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Ideal hardware performance counters provide exact deterministic results. Real-world performance monitoring unit (PMU) implementations do not always live up to this ideal. Events that should be exact and deterministic (such as retired instructions) show run-to-run variation and overcount on x86 64 machines, even when run in strictly controlled environments. These effects are non-intuitive to casual users and cause difficulties when strict determinism is desirable, such as when implementing deterministic replay or deterministic threading libraries.We investigate eleven different x86 64 CPU implementations and discover the sources of divergence from expected count totals. Of all the counter events investigated, we find only a few that exhibit enough determinism to be used without adjustment in deterministic execution environments. We also briefly investigate ARM, IA64, POWER and SPARC systems and find that on these platforms the counter events have more determinism.We explore various methods of working around the limitations of the x86 64 events, but in many cases this is not possible and would require architectural redesign of the underlying PMU.

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“…As processor complexity continues to increase at a rapid rate and microarchitectures continue to become more speculative, it is not clear whether the performance simulators can continue to effectively predict actual machine performance due to several crucial issues: simulator retargetability, simulator validation, simulation speed and simulation accuracy [2]. Moreover, there are only a few analytical models [13,29,38] that provide some insight by isolating important parameters, but still too simple to capture the behavior of a real system.…”

Section: Motivation and Related Workmentioning

confidence: 99%

Modeling And Performance Evaluation Of Branch And Value Prediction In Ilp Processors

Gušev

Mitrevski

2003

International Journal of Computer Mathematics

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Speculative execution is one of the key issues to boost the performance of future generation microprocessors. In this paper, we introduce a novel approach to evaluate the effects of branch and value prediction, which allow the processor to execute instructions beyond the limits of control and true data dependences. Until now, almost all the estimations of their performance potential under different scenarios have been obtained using trace-driven or execution-driven simulation. Occasionally, some simple deterministic models have been used. We employ an analytical model based on recently introduced Fluid Stochastic Petri Nets (FSPNs) in order to capture the dynamic behavior of an ILP processor with aggressive use of prediction techniques and speculative execution.Here we define the FSPN model, derive the state equations for the underlying stochastic process and present performance evaluation results to illustrate its usage in deriving measures of interest. Our implementationindependent stochastic modeling framework reveals considerable potential for further research in this area using numerical solution of systems of partial differential equations and=or discrete-event simulation of FSPN models.

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Can trace-driven simulators accurately predict superscalar performance?

Abstract: PowerPC 620 microprocessor: A high performance superscalar RISC processor. COMPCON 95, 1995.

Cited by 25 publications

References 11 publications

Accurately approximating superscalar processor performance from traces

Accurately approximating superscalar processor performance from traces

Non-determinism and overcount on modern hardware performance counter implementations

Modeling And Performance Evaluation Of Branch And Value Prediction In Ilp Processors

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