C/C++ Based System Design Flow using SpecC, VCC and SystemC

Cai, Lukai; Olivarez, Mike; Kritzinger, Paul; Gajski, Daniel D.

doi:10.1007/0-306-48734-9_15

Cited by 4 publications

(5 citation statements)

References 1 publication

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“…Several C/C++ language based approaches such as SystemC, SpecC are primarily aimed at making the C language usable for hardware and software design and allow efficient and early simulation, synthesis, and/or verification [2]. However, these approaches do not facilitate modeling of applications at a level of abstraction that enables algorithmic analysis.…”

Section: Related Workmentioning

confidence: 98%

A hierarchical approach for energy efficient application design using heterogeneous embedded systems

Mohanty

Prasanna

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application design using heterogeneous embedded systems. However, more choices during application design results in a large design space that must be traversed efficiently. In this paper, we propose a hierarchical methodology that integrates optimization heuristics, high-level performance estimators, and low-level simulators to enable efficient exploration of large design spaces. Our methodology is fast, robust against approximation errors due to high-level modeling, and can evaluate a much larger design space than an optimization heuristic only design space exploration technique. We have augmented MILAN, a model-based integrated simulation framework for embedded systems, to develop an environment to perform hierarchical design space exploration. Using our methodology for a beamforming application, we identify an energy-efficient mapping onto a heterogeneous embedded system while meeting a given latency constraint. We also demonstrate the use of our methodology in identifying an energy and latency efficient heterogeneous embedded system based on user-specified performance requirements for a personnel detection algorithm from a set of devices that includes FPGAs, DSPs, and traditional processors.

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Section: Related Workmentioning

confidence: 98%

A hierarchical approach for energy efficient application design using heterogeneous embedded systems

Mohanty

Prasanna

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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“…Some of them, like the Ptolemy tool [2], don't support a layered abstraction level design approach and use a single specification including both functional behavior and architecture models. Others support the platform-based design approach (like Metropolis [3]) or the top-down design methodology (like SpecC [4]). However, it is demonstrated that the Y-chart layer's based approach, which is followed by several recent works, became nowadays the most popular and used for designing heterogeneous multiprocessors embedded systems.…”

Section: System-level Exploration Tools Comparative Synthesismentioning

confidence: 99%

“…Although the differences among the seven tools are not absolute, the features shown in Table 1 indicate that the most preferable methodologies/tools are Metropolis, VCC [4], and Sesame-like [5,6], because they have the largest amount of positive marks ("+"). By elimination, the Metropolis environment is excluded of the most preferable methodologies list since it does not facilitate explicitly the Y-chart approach.…”

Section: System-level Exploration Tools Comparative Synthesismentioning

confidence: 99%

System-Level Performance Evaluation of Very High Complexity Media Applications : A H264/AVC Encoder Case Study

Zrida¹,

Jemai²,

Ammari³

et al. 2011

IJCNS

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Given the substantially increasing complexity of embedded systems, the use of relatively detailed clock cycle-accurate simulators for the design-space exploration is impractical in the early design stages. Raising the abstraction level is nowadays widely seen as a solution to bridge the gap between the increasing system complexity and the low design productivity. For this, several system-level design tools and methodologies have been introduced to efficiently explore the design space of heterogeneous signal processing systems. In this paper, we demonstrate the effectiveness and the flexibility of the Sesame/Artemis system-level modeling and simulation methodology for efficient peformance evaluation and rapid architectural exploration of the increasing complexity heterogeneous embedded media systems. For this purpose, we have selected a system level design of a very high complexity media application; a H.264/AVC (Advanced Video Codec) video encoder. The encoding performances will be evaluated using system-level simulations targeting multiple heterogeneous multiprocessors platforms

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“…Several C/C++ language based approaches such as SystemC, Handel-C, SpecC are primarily aimed at making the C language usable for hardware and software design and allow efficient and early simulation, synthesis, and/or verification [1], [2]. However, these approaches do not facilitate modeling of kernels at a level of abstraction that enables algorithmic analysis.…”

Section: Related Workmentioning

confidence: 99%

“…Workbench Configuration (1): In this step, the designer analyzes the kernel to define a domain specific model. However, the designer does not derive any of the functions associated with the model.…”

Section: Design Flowmentioning

confidence: 99%

An Algorithm Designer’s Workbench for Platform FPGAs

Mohanty

Prasanna

2003

Field Programmable Logic and Application

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Abstract. Growing gate density, availability of embedded multipliers and memory, and integration of traditional processors are some of the key advantages of Platform FPGAs. Such FPGAs are attractive for implementing compute intensive signal processing kernels used in wired as well as wireless mobile devices. However, algorithm design using Platform FPGAs, with energy dissipation as an additional performance metric for mobile devices, poses significant challenges. In this paper, we propose an algorithm designer's workbench that addresses the above issues. The workbench supports formal modeling of the signal processing kernels, evaluation of latency, energy, and area of a design, and performance tradeoff analysis to facilitate optimization. The workbench includes a high-level estimator for rapid performance estimation and widely used low-level simulators for detailed simulation. Features include a confidence interval based technique for accurate power estimation and facility to store algorithm designs as library of models for reuse. We demonstrate the use of the workbench through design of matrix multiplication algorithm for Xilinx Virtex-II Pro.

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C/C++ Based System Design Flow using SpecC, VCC and SystemC

Cited by 4 publications

References 1 publication

A hierarchical approach for energy efficient application design using heterogeneous embedded systems

A hierarchical approach for energy efficient application design using heterogeneous embedded systems

System-Level Performance Evaluation of Very High Complexity Media Applications : A H264/AVC Encoder Case Study

An Algorithm Designer’s Workbench for Platform FPGAs

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