An Algorithm Designer’s Workbench for Platform FPGAs

Abstract

Abstract. Growing gate density, availability of embedded multipliers and memory, and integration of traditional processors are some of the key advantages of Platform FPGAs. Such FPGAs are attractive for implementing compute intensive signal processing kernels used in wired as well as wireless mobile devices. However, algorithm design using Platform FPGAs, with energy dissipation as an additional performance metric for mobile devices, poses significant challenges. In this paper, we propose an algorithm designer's workbench that addresses the above issues. The workbench supports formal modeling of the signal processing kernels, evaluation of latency, energy, and area of a design, and performance tradeoff analysis to facilitate optimization. The workbench includes a high-level estimator for rapid performance estimation and widely used low-level simulators for detailed simulation. Features include a confidence interval based technique for accurate power estimation and facility to store algorithm designs as library of models for reuse. We demonstrate the use of the workbench through design of matrix multiplication algorithm for Xilinx Virtex-II Pro.

A model-based extensible framework for efficient application design using FPGA

“…However, the major obstacle to widespread use of FPGAs is the lack of highlevel design methodologies and tools [Doucet et al 2002;McGregor et al 1998;Mohanty and Prasanna 2004]. Most available FPGA design tools focus on compilation of a design specified in an HDL onto a target device.…”