A model-based extensible framework for efficient application design using FPGA

Mohanty, Sumit; Prasanna, Viktor K.

doi:10.1145/1230800.1230805

Cited by 9 publications

(7 citation statements)

References 35 publications

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“…Mohanty and Prasanna [18] proposed kernel-level modeling of FPGA algorithms, which is similar to CMD, but their work focused on power-consumption prediction and did not provide clock-frequency prediction methods. Xilinx System Generator [19] shares the same abstract-modeling approach, but, again, clock-frequency prediction is not provided.…”

Section: Background and Related Researchmentioning

confidence: 99%

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Wang

Stitt

Lam

et al. 2015

International Journal of Reconfigurable Computing

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Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many highperformance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD's prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

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Section: Background and Related Researchmentioning

confidence: 99%

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Wang

Stitt

Lam

et al. 2015

International Journal of Reconfigurable Computing

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“…A hierarchical model-based framework for FPGA development in RC is presented by Mohanty and Prasanna [2007] which includes support for evaluation of design alternatives early in the development process. The framework integrates a high-level performance estimator (HiPerE) and a design space exploration tool (DESERT) for efficient evaluation of candidate mappings against user-specified performance requirements onto system-on-chip (SoC) architectures described using the Generic Model (GenM) [Mohanty et al 2002].…”

Section: Background and Related Researchmentioning

confidence: 99%

“…The framework integrates a high-level performance estimator (HiPerE) and a design space exploration tool (DESERT) for efficient evaluation of candidate mappings against user-specified performance requirements onto system-on-chip (SoC) architectures described using the Generic Model (GenM) [Mohanty et al 2002]. While the framework in Mohanty and Prasanna [2007] overlaps to some degree with this research, there are several key differences. First, the framework in Mohanty and Prasanna [2007] is intended to serve as a development environment, unlike RCML which is a modeling environment designed for estimation-level modeling of RC systems.…”

Section: Background and Related Researchmentioning

confidence: 99%

RCML

Reardon

Holland

George

et al. 2012

ACM Trans. Embed. Comput. Syst.

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Reconfigurable computing (RC) is emerging as a promising area for embedded computing, in which complex systems must balance performance, flexibility, cost, and power. The difficulty associated with RC development suggests improved strategic planning and analysis techniques can save significant development time and effort. This article presents a new abstract modeling language and environment, the RC Modeling Language (RCML), to facilitate efficient design space exploration of RC systems at the estimation modeling level, that is, before building a functional implementation. Two integrated analysis tools and case studies, one analytical and one simulative, are presented illustrating relatively accurate automated analysis of systems modeled in RCML.

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“…A hierarchical model-based framework for FPGA development is presented by Mohanty and Prasanna [2007] intended to support evaluation of design alternatives early in the design process. The framework integrates a high-level performance estimator (HiPerE) and a design space exploration tool (DESERT) for efficient evaluation of candidate mappings against user-specified performance requirements onto architectures that can be described using the Generic Model (GenM) for System-on-Chip (SoC) architectures [Mohanty et al 2002].…”

Section: Background and Related Researchmentioning

confidence: 99%

A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems

Reardon¹,

Grobelny²,

George³

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

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Reconfigurable computing (RC) is rapidly emerging as a promising technology for the future of high-performance and embedded computing, enabling systems with the computational density and power of custom-logic hardware and the versatility of software-driven hardware in an optimal mix. Novel methods for rapid virtual prototyping, performance prediction, and evaluation are of critical importance in the engineering of complex reconfigurable systems and applications. These techniques can yield insightful tradeoff analyses while saving valuable time and resources for researchers and engineers alike. The research described herein provides a methodology for mapping arbitrary applications to targeted reconfigurable platforms in a simulation environment called RCSE. By splitting the process into two domains, the application and simulation domains, characterization of each element can occur independently and in parallel, leading to fast and accurate performance prediction results for large and complex systems. This article presents the design of a novel framework for system-level simulative performance prediction of RC systems and applications. The article also presents a set of case studies analyzing two applications, Hyperspectral Imaging (HSI) and Molecular Dynamics (MD), across three disparate RC platforms within the simulation framework. The validation results using each of these applications and systems show that our framework can quickly obtain performance prediction results with reasonable accuracy on a variety of platforms. Finally, a set of simulative case studies are presented to illustrate the various capabilities of the framework to quickly obtain a wide range of performance prediction results and power consumption estimates. G. 2010. A simulation framework for rapid analysis of reconfigurable computing systems.

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A model-based extensible framework for efficient application design using FPGA

Cited by 9 publications

References 35 publications

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

RCML

A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems

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