Buried Power SRAM DTCO and System-Level Benchmarking in N3

Salahuddin, Shairfe Muhammad; Perumkunnil, Manu; Litta, E. Dentoni; Gupta, Anshul; Weckx, Pieter; Ryckaert, Julien; Na, M.-H.; Spessot, A.

doi:10.1109/vlsitechnology18217.2020.9265076

Cited by 9 publications

(10 citation statements)

References 1 publication

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“…N3 FinFET SRAM suffers from a large bitline (BL) resistance (RBL) due to the crowded metal tracks in an aggressively scaled cell height (Figure 3). Thus, the buried power rail (BPR) technique is proposed [14] to open up space for signal placements by moving the power delivery network (PDN) from the frontside to the backside. As shown in Figure 2 and 3, the RBL and wordline (WL) resistance (RWL) of A14 NSFET SRAM are reduced compared to N3 FinFET SRAM due to BPR application.…”

Section: Sram Scaling Roadmapmentioning

confidence: 99%

DTCO of sequential and monolithic CFET SRAM

Liu

Salahuddin

Chan

et al. 2023

DTCO and Computational Patterning II

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Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Åcompatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions.

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Section: Sram Scaling Roadmapmentioning

confidence: 99%

DTCO of sequential and monolithic CFET SRAM

Liu

Salahuddin

Chan

et al. 2023

DTCO and Computational Patterning II

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“…In sub-10 nm nodes, the increased RBL would amplify the effect of CBL. Furthermore, a typical access time for SRAM in L1 and L2 cache is below 1 ns [2][3][4][5]. The maximum SBL is therefore around -VDD V/ns without NBL, which implies that the parasitic capacitance needs to be considered for write margin calculation in sub-10 nm nodes.…”

Section: Impact Of Different Operating Frequenciesmentioning

confidence: 99%

“…Continued geometric scaling of devices with advanced CMOS technology increases process variation and enhances driver strength of PMOS transistors [1][2][3][4][5]. These are becoming the major sources that degrade the write ability of static random-access memory (SRAM) [1].…”

Section: Introductionmentioning

confidence: 99%

“…To improve the write ability of SRAMs, circuit assist techniques such as negative bitline (NBL) have been introduced [1][2][3][4]. However, the writeability enhancement with NBL is still limited by the rapidly increasing bitline resistance in sub-10nm technology nodes due to metal geometric scaling and surface scattering [4,5]. The value of write driver voltage with NBL assist circuit can be controlled by a boosting capacitor (Cboost) [1].…”

Section: Introductionmentioning

confidence: 99%

“…Otherwise, an increased data flip time or write failure may incur. Note that a typical range for BL parasitic resistance (RBL) and capacitance (CBL) would be 10 to 100 Ω/cell and below 50aF/cell, respectively [5]. Therefore, RBL of 20 and 40 Ω/cell, and CBL of 25 and 50 aF/cell are taken as references in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

Liu

Salahuddin

Abdi

et al. 2022

IEEE Trans. Electron Devices

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An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this paper. Increased bitline (BL) resistance in sub-10nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate transistors on write margin considering the negative bitline (NBL) assist technique.

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