Built-in self test of high speed analog-to-digital converters

Abstract

high conversion rates are required. With advances of the CMOS technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT), and to collect and analyse their responses. With high conversion rates it is difficult to interface the ADCs to the test instruments due: extra parasitics, line trace mismatches, interferences within the printed circuit board (PCB), and the instrument test probes. This becomes even more challenging in the case of systems-on-a-chip, system-in-a-package, and three-dimensional (3D) chips, where the accessibility of the ADCs for testing purposes is restricted [6]. In this paper we discuss the use of built-in self-test (BIST) techniques for testing high speed ADCs and we present a specific solution, in which the analog input signal and the clock are generated internally. BIST for High Speed ADCs Using advanced CMOS technologies, the cost per transistor decreases and integrated solutions become competitive. Thus, more specific functionalities can be fully integrated on-chip. Moreover, the reliability of the manufacturing process maintains high, allowing reliable function to be implemented on-chip as well. The implementation of test-related functions directly on-chip during the IC design phase, which is called design for testability, evolved firstly for purely digital ICs and then migrated to mixed-signal devices. Using a BIST approach contributes to additional area, increases design time and effort, and may degrade the performance of the DUT due to intrusive test structures. Table 1 summarizes the pros and cons of a BIST solution. * Do not deal with the clock signal generation. † Area of the read-only memory not included. ‡ SFDR measured at 1 MHz frequency. § Ignoring PLLs reference spurs. * * Jitter rms integrated above 1 MHz and estimated from simulation.

Enhancing the Accuracy and Speed of Sampling in Image Sensors by Designing Analog to Digital Converter with Power Decrease Approach

“…In [3], offset error compensation is done by adjusting the voltage of the body of preamplifier-class even-entry transistor. To this purpose, each comparer has an offset calibration circuit (OSCAL).…”

“…Another utilizations of these circuits can be found in orbits due to image processing in [1][2][3][4][5].…”

“…One of the most significant utilizations is the medical industry, which, due to CMOS ability in the performance of low power image sensors and in a very small area, can play a significant role in the advancement of novel medical instruments and equipment. Besides, the novel utilizations of image sensors like mobile phones, cars, military industries, wireless sensor networks, and IoT have made this one of the most significant problems in modern electronic industries and systems [3].…”