Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach

Rajendran, Jeyavijayan; Sinanoglu, Ozgur; Karri, Ramesh

doi:10.1109/tvlsi.2016.2530092

Cited by 63 publications

(26 citation statements)

References 41 publications

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“…They include enclaves for trusted execution, like the industrial ARM TrustZone and Intel SGX or the academic MIT Sanctum (these and others are reviewed in [5]), wrappers for monitoring and cross-checking of untrusted third-party intellectual property (IP) modules [6], centralized IP infrastructures for secure system design [7], verification of computation [8], secure task scheduling [9], secure network-on-chip (NoC) architectures [10], etc. Besides, there are also design-time mitigation schemes, e.g., using high-level synthesis strategies for detection, collusion prevention, and isolation of malicious IP [11].…”

Section: Hardware Security Featuresmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

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Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware-and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

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Section: Hardware Security Featuresmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

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“…Detectability: We now discuss the available detection techniques from the defender's perspective, and the anti-detection capability from the attacker's perspective. Pre-silicon detection methods, e.g.formal verification, code analysis, are usually utilized to detect HTs in 3PIP cores (61). Previous researches (62; 32; 63) have proposed hardware description language (HDL) code analysis, or structural analysis techniques for soft IP cores.…”

Section: Pip Vendor Attacksmentioning

confidence: 99%

Ten years of hardware Trojans: a survey from the attacker's perspective

Xue

Liu

et al. 2020

IET Computers & Digital Techniques

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In the last decade, hardware Trojan has emerged as a serious concern in integrated circuit (IC) industry. As such, hardware Trojan detection techniques have been studied extensively. However, in order to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. In this paper, we attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, we study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities and challenges when he designs and implements a hardware Trojan. Particularly, the following questions are explored. What are the current methods and capabilities of attackers after ten years of research and development? By considering more and more sophisticated hardware Trojan detection techniques, what challenges do the attackers face, and vice versa? First, we present adversarial models in terms of the adversary's methods, adversary's capabilities and adversary's challenges in seven practical hardware Trojan implementation scenarios: in-house design team attacks, third-party intellectual property (3PIP) vendor attacks, computer-aided design (CAD) tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field programmable gate array (FPGA) Trojan attacks. Second, we analyze the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility (the practicality of the attacks), detectability (anti-detection capability of that kind of Trojan), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are discussed. This paper also presents several new insights and assumptions for the first time, including considering the Trojans not only from the copyright owner's perspective, but also from the users' perspective, and discussing the hardware Trojan attacks in the testing phase and in the distribution phase. This paper can hopefully provide a reference for future works on building effective hardware Trojan defenses.

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“…Recent research explores how HLS can design IP components with enhanced security features, while minimizing the overhead [14]. HLS-based techniques have been used to build a trustworthy system using untrustworthy third party IPs (3PIPs) [15], [16]. HLS was also used for HT detection and recovery [13], [17].…”

Section: B Security-aware Hlsmentioning

confidence: 99%

High-Level Synthesis of Benevolent Trojans

Pilato

Basu

Shayan

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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High-Level Synthesis (HLS) allows designers to create a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). HLS reduces engineering effort and design-time errors, allowing the integration of additional features. This study introduces an approach to generate benevolent Hardware Trojans (HT) using HLS. Benevolent HTs are Intellectual Property (IP) watermarks that borrow concepts from well-known malicious HTs to ward off piracy and counterfeiting either during the design flow or in fielded integrated circuits. Benevolent HTs are difficult to detect and remove because they are intertwined with the functional units used to implement the IP. Experimental results testify to the suitability of the approach and the limited overhead.

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Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach

Cited by 63 publications

References 41 publications

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Ten years of hardware Trojans: a survey from the attacker's perspective

High-Level Synthesis of Benevolent Trojans

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