Building a high-performance, programmable secure coprocessor

Smith, Sean W.; Weingart, Steve H.

doi:10.1016/s1389-1286(98)00019-x

Cited by 202 publications

(87 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are systems available to provide such tamper-resistance. For example, IBM's PCI Cryptographic Coprocessor, encapsulates a 486-class processing subsystem within a tampersensing and tamper-responding environment where one can run security-sensitive processes [SW99]. Smart cards also incorporate barriers to protect the hidden key(s), many of which have been broken [And01].…”

Section: Digital Pufmentioning

confidence: 99%

Controlled Physical Random Functions

Gassend¹,

Dijk²,

Clarke³

et al. 2007

Security With Noisy Data

155

271

View full text Add to dashboard Cite

show abstract

Section: Digital Pufmentioning

confidence: 99%

Controlled Physical Random Functions

Gassend¹,

Dijk²,

Clarke³

et al. 2007

Security With Noisy Data

155

271

View full text Add to dashboard Cite

show abstract

“…Another approach is to use secure co-processors (e.g. [59,64]) which "sign" the computation as correct, under the assumption that the adversary cannot tamper with the processor. Finally, other trust models have been considered.…”

Section: Related Workmentioning

confidence: 99%

Verifiable Delegation of Computation over Large Datasets

Benabbas

Gennaro²,

Vahlis

2011

Lecture Notes in Computer Science

268

282

View full text Add to dashboard Cite

We study the problem of computing on large datasets that are stored on an untrusted server. We follow the approach of amortized verifiable computation introduced by Gennaro, Gentry, and Parno in CRYPTO 2010. We present the first practical verifiable computation scheme for high degree polynomial functions. Such functions can be used, for example, to make predictions based on polynomials fitted to a large number of sample points in an experiment. In addition to the many non-cryptographic applications of delegating high degree polynomials, we use our verifiable computation scheme to obtain new solutions for verifiable keyword search, and proofs of retrievability. Our constructions are based on the DDH assumption and its variants, and achieve adaptive security, which was left as an open problem by Gennaro et al (albeit for general functionalities).Our second result is a primitive which we call a verifiable database (VDB). Here, a weak client outsources a large table to an untrusted server, and makes retrieval and update queries. For each query, the server provides a response and a proof that the response was computed correctly. The goal is to minimize the resources required by the client. This is made particularly challenging if the number of update queries is unbounded. We present a VDB scheme based on the hardness of the subgroup membership problem in composite order bilinear groups. This is the first such construction that relies on a "constant-size" assumption, and does not require expensive generation of primes per operation.

show abstract

“…The conventional approach to building physically secure systems (Smith and Weingart, 1999;Yee, 1994) is to encase the entire system in a tamperproof package. For example, the IBM 4758 cryptographic coprocessor contains an Intel 486 processor, a special chip for cryptographic operations, and memory modules (DRAM, flash, etc.)…”

Section: Tamper-proof Packagesmentioning

confidence: 99%

Aegis: A single-chip secure processor

Suh¹,

O'Donnell²,

Devadas³

2007

IEEE Des. Test. Comput.

View full text Add to dashboard Cite

This article presents the AEGIS secure processor architecture, which enables new applications by ensuring private and authentic program execution even in the face of physical attack. Our architecture uses two new primitives to achieve physical security. First, we describe Physical Random Functions which reliably protect and share secrets in a manner that is cheaper and more secure than existing solutions based on non-volatile memory. Second, off-chip memory protection mechanisms ensure the integrity and the privacy of off-chip memory. Our processor, with its new protection mechanisms, has been implemented on an FPGA, and is fully functional. We briefly assess the cost of the security mechanisms in our processor and show that it is reasonable. ª

show abstract

Building a high-performance, programmable secure coprocessor

Cited by 202 publications

References 12 publications

Controlled Physical Random Functions

Controlled Physical Random Functions

Verifiable Delegation of Computation over Large Datasets

Aegis: A single-chip secure processor

Contact Info

Product

Resources

About