2007
DOI: 10.1109/mdt.2007.4343587
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Aegis: A single-chip secure processor

Abstract: This article presents the AEGIS secure processor architecture, which enables new applications by ensuring private and authentic program execution even in the face of physical attack. Our architecture uses two new primitives to achieve physical security. First, we describe Physical Random Functions which reliably protect and share secrets in a manner that is cheaper and more secure than existing solutions based on non-volatile memory. Second, off-chip memory protection mechanisms ensure the integrity and the pr… Show more

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Cited by 18 publications
(18 citation statements)
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“…Our current design for an oblivious execution framework is SGX-specific. However, we believe its design characteristics and optimization techniques are general, which can be applied to other trusted platforms such as AEGIS [51], Ascend [52], XOM [53], Bastion [54], Sanctum [55]. For example, our register-based stash ( §V-B1) can be considered as a generic optimization for ORAM, if the underlying trust architecture shares any of memory-related subsystem such as cache, TLB, MMU, and DRAM.…”
Section: Discussionmentioning
confidence: 99%
“…Our current design for an oblivious execution framework is SGX-specific. However, we believe its design characteristics and optimization techniques are general, which can be applied to other trusted platforms such as AEGIS [51], Ascend [52], XOM [53], Bastion [54], Sanctum [55]. For example, our register-based stash ( §V-B1) can be considered as a generic optimization for ORAM, if the underlying trust architecture shares any of memory-related subsystem such as cache, TLB, MMU, and DRAM.…”
Section: Discussionmentioning
confidence: 99%
“…The state-of-the-art secure processor, AEGIS [2], was designed to only reveal the data inside the processor. Therefore any data leaving the processor is encrypted.…”
Section: A Plaintext Processingmentioning
confidence: 99%
“…However, in reality the only entity that can be truly trusted is the user themselves. A physical approach to privacy preserving data processing is with Field-Programmable Gate Arrays (FPGAs) and custom hardware, which bestow greater security and privacy over their software alternatives [2] [3]. We propose Secure FPGA as a Service (SFaaS) to leverage these security properties of FPGAs to harden the cloud against both insider and outsider threats.…”
Section: Introductionmentioning
confidence: 99%
“…Architectural support for physical RAM privacy. There have been many designs for encrypting physical memory to counter physical attacks (e.g., [34,35,36,21,37,18,38,39,40,41]). Representation examples are: 1) protecting data privacy by performing decryption in parallel to memory access [21]; 2) protecting data privacy and integrity in distributed shared memory multi-processors systems [39] by adapting the Galois/Counter Mode of operation with the counter-mode encryption [38], or by using the address independent counter-mode encryption and Merkle tree built on top of the counters [42]; 3) preventing secret leakage against intrusive memory attack by integrating secret sharing and coding based schemes [40]; 4) a hybrid hardware-software approach to full system security named SecureME [41].…”
Section: Related Workmentioning
confidence: 99%