Bridging the testing speed gap: design for delay testability

Speek, H.; Kerkhoff, Hans G.; Sachdev, Manoj; Shashaani, M.

doi:10.1109/etw.2000.873771

Cited by 5 publications

(4 citation statements)

References 15 publications

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“…Indeed, pipelined and superscalar designs demonstrated to be random pattern resistant [2]. The use of hardware-based approaches, such as scan chains and BIST, even though consolidated in industry for integrated digital circuits, has proven to be often inadequate, since these techniques introduce excessive area overhead [1], require extreme power dissipation during the test application [13], and are often ineffective when testing delay-related faults [12].…”

Section: Introductionmentioning

confidence: 99%

Evolution of Test Programs Exploiting a FSM Processor Model

Sánchez

Squillero

Tonda

2011

Applications of Evolutionary Computation

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Microprocessor testing is becoming a challenging task, due to the increasing complexity of modern architectures. Nowadays, most architectures are tackled with a combination of scan chains and Software-Based Self-Test (SBST) methodologies. Among SBST techniques, evolutionary feedback-based ones prove effective in microprocessor testing: their main disadvantage, however, is the considerable time required to generate suitable test programs.A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to timeexpensive simulations on low-level models. Experimental results, performed on an OpenRISC processor, show that the resulting test obtains a nearly complete fault coverage against the targeted fault model.

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Section: Introductionmentioning

confidence: 99%

Evolution of Test Programs Exploiting a FSM Processor Model

Sánchez

Squillero

Tonda

2011

Applications of Evolutionary Computation

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“…This architecture and its components have been described in detail and simulated in VHDL at system level and using HSPICE data for different blocks in previous work [3,4]. In this paper, the complete architecture has been simulated at circuit level, making use of HSPICE and using the 0.35 pm TSMC CMOS technology from MOSIS [12].…”

Section: The Dfdt Structure Usedmentioning

confidence: 99%

“…In this paper, the complete architecture has been simulated at circuit level, making use of HSPICE and using the 0.35 pm TSMC CMOS technology from MOSIS [12]. Readers are referred to [3,4,11] for more details on previous results. …”

Section: The Dfdt Structure Usedmentioning

confidence: 99%

Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations

Vermaak

Kerkhoff²

IEEE European Test Workshop, 2001.

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Recently, a new type of Design-for-Delay-Testability structure and associated Built-In Self-Test architecture for detecting delay faults in digital high-performance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the susceptibility of the proposed structure to process-and application-induced variations has been investigated Due to the critical timing necessary when detecting small delay faults it is crucial to know what to expect +om these variations and subsequently reduce their influence.

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“…Scan test does not excite fault conditions in a real-life environment (power, ground stress and noise). At-speed delay testing is severely constrained by the employed Automatic Test Equipment (ATE) features, which are frequently outpaced by new manufactured products (Speek, 2000). Conversely, due to the increased controllability achieved on the circuit, atspeed scan-based delay testing may identify as faulty some resources that would never affect the system's behavior (false paths) (Chen, 1993), thereby leading to yield loss.…”

Section: Introductionmentioning

confidence: 99%

Software-Based Self-Test of Embedded Microprocessors

Bernardi

Grosso

Sanchez

et al.

Design and Test Technology for Dependable Systems-on-Chip

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In the recent years, the usage of embedded microprocessors in complex SoCs has become common practice. Their test is often a challenging task, due to their complexity, to the strict constraints coming from the environment and the application, and to the typical SoC design paradigm, where cores (including microprocessors) are often provided by third parties, and thus must be seen as black boxes. An increasingly popular solution to this challenge is based on developing a suitable test program, forcing the processor to execute it, and then checking the produced results (Software-Based Self Test, or SBST). The SBST methodology is particularly suitable for being applied at the end of manufacturing and in the field as well, to detect the occurrence of faults caused by environmental stresses and intrinsic aging (e.g., negative bias temperature instability, hot carriers injection) in embedded systems. This chapter provides an overview of the main techniques proposed so far in the literature to effectively generate test programs, ranging from manual ad hoc techniques to automated and general ones. Some details about specific hardware modules that can be fruitfully included in a SoC to ease the test of the processor when the SBST technique is adopted are also provided.

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Bridging the testing speed gap: design for delay testability

Cited by 5 publications

References 15 publications

Evolution of Test Programs Exploiting a FSM Processor Model

Evolution of Test Programs Exploiting a FSM Processor Model

Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations

Software-Based Self-Test of Embedded Microprocessors

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