Bridging the Processor-Memory Performance Gapwith 3D IC Technology

Abstract

MICROPROCESSOR PERFORMANCE has been improving at roughly 60% per year. Memory access times, however, have improved by less than 10% per year. 1 The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures that support out-of-order and speculative execution. Moreover, processors have been designed with increasingly large cache hierarchies to hide main memory latency. This article examines how 3D IC technology can improve interactions between the processor and memory.Three-dimensional ICs, as shown in Figure 1, consist of planar device layers stacked one atop another and interconnected by short, vertical wires. 2 With the end of conventional device scaling in sight, 3D ICs let scaling continue by shifting the focus from device scaling to circuit and system scaling. By stacking multiple planar device layers with short, vertical separations, designers can build systems that exhibit lower interconnect latencies; higher packing densities of logic, memory, and other circuits; and heterogeneous integration of circuits of different materials (for example, CMOS, SiGe, and III-V), signals (digital, analog, and RF), or technologies (microelectromechanical systems, optics, and so forth). In addition to lower wire latency through shorter paths, 3D IC technology offers

Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system

“…Various mechanisms have been proposed to exploit memory bandwidth and improve the cache performance ( [3] and [4]). The stream buffer proposed in [5] and [6] is one of the most efficient structures to exploit memory bandwidth and reduce memory access latency.…”

“…The latency of the 2D off-chip memory is obtained from an actual x86 processor system by using LMbench tool [13]. The access latency of 3D stacked memory is obtained with the assumption for high bandwidth as used in [3] and [14]. The multi-way stream buffer is used and has 16-entries for each way as in [3].…”

Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology

“…In [5], Woo et al proposed a SMART-3D architecture, which efficiently utilized the TSVs to reduce long latency of fetching and write-back in an L2 cache. Liu et al [6] investigated various conventional schemes including a stream buffer to bridge the processor and memory performance gap based on the 3-D ICs. This paper introduces versatile stream buffer architecture with a victim cache to exploit massive memory bandwidth and to reduce memory traffic.…”

Leveraging 3D Technology for Improved Reliability

“…Some of this attention has focused on implementing a cache in 3D [25,29,40], even in the context of a multi-core NUCA layout [16]. Few studies have considered using additional dies entirely for SRAM or DRAM [2,17,18].…”