MICROPROCESSOR PERFORMANCE has been improving at roughly 60% per year. Memory access times, however, have improved by less than 10% per year. 1 The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures that support out-of-order and speculative execution. Moreover, processors have been designed with increasingly large cache hierarchies to hide main memory latency. This article examines how 3D IC technology can improve interactions between the processor and memory.Three-dimensional ICs, as shown in Figure 1, consist of planar device layers stacked one atop another and interconnected by short, vertical wires. 2 With the end of conventional device scaling in sight, 3D ICs let scaling continue by shifting the focus from device scaling to circuit and system scaling. By stacking multiple planar device layers with short, vertical separations, designers can build systems that exhibit lower interconnect latencies; higher packing densities of logic, memory, and other circuits; and heterogeneous integration of circuits of different materials (for example, CMOS, SiGe, and III-V), signals (digital, analog, and RF), or technologies (microelectromechanical systems, optics, and so forth). In addition to lower wire latency through shorter paths, 3D IC technology offers

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We report significant crosstalk reduction between two transistor planes in 3D integrated circuits (3D ICs) using tungsten ground plane structures as the isolation layer. Simulation and experimental results show ~8 dB of crosstalk attenuation. A significant conclusion of our study is that a ground plane that physically shadows the region it is isolating is optimum for deriving most of the benefits of isolation. We also show that for ground planes composed of standard MOS metallizations, i.e. W, Al, Cu, similar crosstalk isolation is expected. The inter-device ground plane structures has potential to be a standard isolation technology for 3D mixed-signal and RF integrated systems due to simple fabrication and significant crosstalk attenuation. I. INTRODUCTIONThree-dimensional (3D) integration technology allows fabrication of planar devices and circuits in vertically stacked planes. The main advantages of 3D integration over 2D implementation are in high device density, novel integration opportunities, and improved routing and interconnections [1][2][3][4][5]. There have been numerous experimental demonstrations, utilizing a variety of approaches where wafer-scale device layer of thickness of the order of micro-meters have been successfully transplanted onto a "host wafer" [5-8] to form a 3D integrated system. With increasing emphasis on mobile and high frequency applications, mixed-signal 3D integration provides an important technical approach towards achieving high performance and compact architectures, easier design, and powerful and novel system-on-chip application applications. Noise and crosstalk, due to coupling between analog and digital elements, are the major physical mechanisms that hinder the integration of highly sensitive analog/RF circuits with fast switching digital circuits. This crosstalk and noise issue becomes more pronounced as clock frequencies and logic speeds continue to rise and analog systems continue to improve in high frequency characteristics. Ground planes used in 3D integration provide a possible path to suppressing this crosstalk and achieving the promising potential of high performance. This suppression of crosstalk, using ground planes in 3D integration, is the focus of this paper.For conventional 2D mixed-signal applications, a number of techniques have been developed to improve crosstalk isolation. Porous silicon trenches [9], highly-doped pocketed structures [10], Faraday cages [11], and guard rings [12] are among the methods by which varying degrees of improvement have been achieved. These techniques are difficult to

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