2012
DOI: 10.1109/led.2012.2188492
|View full text |Cite
|
Sign up to set email alerts
|

Breakdown-Voltage-Enhancement Technique for RF-Based AlGaN/GaN HEMTs With a Source-Connected Air-Bridge Field Plate

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
24
0

Year Published

2013
2013
2023
2023

Publication Types

Select...
6
1

Relationship

0
7

Authors

Journals

citations
Cited by 76 publications
(24 citation statements)
references
References 7 publications
0
24
0
Order By: Relevance
“…Field-plate structures have been applied to AlGaN/GaN HEMTs [23][24][25][26][27] to mitigate the concentration of electric field at the gate edge of the drain side, which is effective in reducing the current collapse. However, several reliability issues still remain in GaN HEMTs.…”
Section: Introductionmentioning
confidence: 99%
“…Field-plate structures have been applied to AlGaN/GaN HEMTs [23][24][25][26][27] to mitigate the concentration of electric field at the gate edge of the drain side, which is effective in reducing the current collapse. However, several reliability issues still remain in GaN HEMTs.…”
Section: Introductionmentioning
confidence: 99%
“…So, C gs , C gd , and C ds should be used to represent the intrinsic capacitances of intrinsic FET part. For the case shown in Figure 1B, the source‐connected FP structure slightly reduces C gd but at the cost of an increase in C gs . 14 To verify this point, the extracted total capacitances C gst , C gd , and C dst for 2 × 100 μm GaN device with NFP/FP structures under cold pinch‐off condition are given in Figure 3. For the case of NFP GaN device, C gst = 105.9 fF and C gd = 96.4 fF.…”
Section: Capacitance Partitioning Characteristics Of Cold Pinch‐off Gmentioning
confidence: 87%
“…Also, it is worth noting that the above assumptions are probably only applicable in the non‐field‐plate (NFP) GaN devices, as shown in Figure 1A. To enhance the breakdown voltage and suppress the current collapse, a field‐plate (FP) structure is used, 14,15 and a typical example is shown in Figure 1B. Moreover, to further improve the breakdown voltage and reduce the on‐resistance, the gate‐drain spacing L GD is increased, and the gate‐source spacing L GS is reduced, which results in an asymmetric structure of GaN device 16,17 .…”
Section: Introductionmentioning
confidence: 99%
“…While manipulating the electric field, implementing FPs also introduces parasitic capacitance (e.g., C GD and C DS ), which may compromise the high frequency and switching performance of the device. [ 245 ] Therefore, a few unique FP structures were proposed, such as floating grating FPs [ 246 ] and air‐bridge FP, [ 247 ] to reduce the parasitic capacitance. A slant‐shaped FP was also applied to smoothen the electric field profile and increase the device V BD .…”
Section: Electric Field Manipulationmentioning
confidence: 99%