Branch folding in the CRISP microprocessor: reducing branch delay to zero

Ditzel, David R.; McLellan, Hubert R.

doi:10.1145/30350.30351

Cited by 88 publications

(18 citation statements)

References 16 publications

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“…This contrasts with the superscalar which relies on branch prediction to significantly reduce the cost of conditional branching. Moreover superscalar microarchitectures may rely on branch folding [12] to execute many branches with truly zero cost. In ASH control-flow graph join points also require to extra machinery, namely SWITCH, MU, and MUX nodes.…”

Section: Synchronization Overheadmentioning

confidence: 99%

Dataflow: A Complement to Superscalar

Budiu

Artigas

Goldstein

2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

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There has been a resurgence of interest in dataflow architectures, because of their potential for exploiting parallelism with low overhead. In this paper we analyze the performance of a class of static dataflow machines on integer media and control-intensive programs and we explain why a dataflow machine, even with unlimited resources, does not always outperform a superscalar processor on general-purpose codes, under the assumption that both machines take the same time to execute basic operations. We compare a program-specific dataflow machine with unlimited parallelism to a superscalar processor running the same program. While the dataflow machines provide very good performance on most data-parallel programs, we show that the dataflow machine cannot always take advantage of the available parallelism. Using the dynamic critical path we investigate the mechanisms used by superscalar processors to provide a performance advantage and their impact on a dataflow model.

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Section: Synchronization Overheadmentioning

confidence: 99%

Dataflow: A Complement to Superscalar

Budiu

Artigas

Goldstein

2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

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“…The architecture of the CRISP microprocessor [Ditzel and McLellan 1987] is a recent attack on the problems of control transfers and embodies an interesting combination of hardware and software techniques: Branch Prediction, Branch Spreading, and Branch Folding. The branch prediction is static and involves the use of a single bit that is set by the compiler according to some heuristics.…”

Section: '9mentioning

confidence: 99%

On the design and performance of conventional pipelined architectures

Topham

Omondi

1988

J Supercomput

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Pipelining is a widely used technique for implementing architectures that have inherent temporal parallelism when there is an operational requirement for high throughput. Many variations on the basic theme have been proposed, with varying degrees of success. The aim of this paper is to present a critical review of conventional pipelined architectures and put some well-known problems in sharp relief. It is argued that conventional pipelined architectures have underlying limitations that can only be dealt with by adopting a different view of pipelining. These limitations are explained in terms of discontinuities in the flow of instructions and data, an d representative machines are examined in support of this argument. In a companion paper [Topham, Omondi and Ibbett, 1988] we examine an alternative approach to the design of pipelined architectures and introduce an alternative theory of pipelining, which we call Context Flow.

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“…In pipelined processors, the condition evaluation has to be delayed until all the instructions that modify the condition codes and precede the branch have finished its execution. The condition evaluation is the most important dependency that restricts the execution of branches with zero delay [7].…”

Section: Some Applicationsmentioning

confidence: 99%

Evaluating 'A+B=K' conditions in constant time

Cortadella

Llaberi

1988., IEEE International Symposium on Circuits and Systems

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THEORETICAL BASISOne of the most important components of an ALU is the adder. Its response time is mainly determined by the carry propagation delay. Evaluation of conditions between two numbers are usually performed with the ALU by means of a substraction. In this paper we deal with a type of conditions that can be evalauted without requiring a complete ALU operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, avoiding the carry propagation delay. Some applications for this circuit are also presented.

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Branch folding in the CRISP microprocessor: reducing branch delay to zero

Cited by 88 publications

References 16 publications

Dataflow: A Complement to Superscalar

Dataflow: A Complement to Superscalar

On the design and performance of conventional pipelined architectures

Evaluating 'A+B=K' conditions in constant time

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