BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective

Abstract

Till date, the existing understanding of negative differential resistance (NDR) is obtained from metal-ferro–metal–insulator–semiconductor (MFMIS) FET, and it has been utilized for both MFMIS and metal–ferro–insulator–semiconductor (MFIS) based NCFETs. However, in MFIS architecture, the ferroelectric capacitance (C FE) is not a lumped capacitance. Therefore, for MFIS negative capacitance (NC) devices, the physical explanation which governs the NDR mechanism needs to be addressed. In this work, for the first time, we present the first principle explanation of the NDR effect in MFIS NC FDSOI. We found that the output current variation with the drain to source voltage (V DS), (i.e. g ds) primarily depends upon two parameters: (a) V DS dependent inversion charge gradient (∂n/∂ V DS); (b) V DS sensitive electron velocity (∂v/∂ V DS), and the combined effect of these two dependencies results in NDR. Further, to mitigate the NDR effect, we proposed the BOX engineered NC FDSOI FET, in which the buried oxide (BOX) layer is subdivided into the ferroelectric (FE) layer and the SiO2 layer. In doing so, the inversion charge in the channel is enhanced by the BOX engineered FE layer, which in turn mitigates the NDR and a nearly zero g ds with a minimal positive slope has been obtained. Through well-calibrated TCAD simulations, by utilizing the obtained positive g ds, we also designed a V DS independent constant current mirror which is an essential part of analog circuits. Furthermore, we discussed the impact of the FE parameter (remanent polarization and coercive field) variation on the device performances. We have also compared the acquired results with existing literature on NC-based devices, which justifies that our proposed structure exhibits complete diminution of NDR, thus enabling its use in analog circuit design.

Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack

“…Recently, Chauhan et al [14] have suggested an interesting approach towards mitigating the negative differential resistance (NDR) effect, usually seen in NCFETs, through the inclusion of a ferroelectric material in the buried oxide of a NC (negative capacitance) FDSOI (fully-depleted silicon-oninsulator) MOSFET, at a gate length of 20 nm, without reporting scaling of the power supply voltage, typically seen with the introduction of a ferroelectric material in the gate stack. Despite reporting high intrinsic gain [14], the incorporation of a ferroelectric layer in the buried oxide (BOX) might have challenges in terms of achieving the desired thickness and interface properties with the SOI channel, which could have further implications in terms of the hysteresis in the transfer characteristics and the scalability of these NCFETs. Therefore, an important aspect to be considered in the analysis of NCFETs could be to ensure that in determining the optimal Ferroelectric layer thickness, both NDR effects in the output characteristics [15] and hysteresis effects in the transfer characteristics [16][17][18] are effectively considered.…”

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

“…The increase in the gate voltage (V GS ) increases the internal voltage amplification due to NC property of the FE layer; thus, the channel charge increases. Therefore, the total gate capacitance (C gg ) increases with V GS , as shown in figure 4(b) [8,9]. Here C gg is the series combination of FE layer and SiO 2 layer capacitances.…”

“…This bestows the steep slope characteristics (i.e. SS < 60 mV decade −1 ), higher ON current (I ON ), and improved switching speed compared to the baseline (BL) FET [5][6][7][8][9]. However, in the nanoscale devices, employing the conventional perovskite materials as a FE layer was challenging due to poor compatibility with CMOS fabrication flow.…”

Gradient voltage amplification effect in FDSOI NCFET with thickness-variable ferroelectric layer

“…The 2D thin film channel is also considered because it's excellent ability in achieving steep SS and large I ON /I OFF ratio [9][10][11]. The special structure such as T-shaped gate NCFET [12], highly-doped double-pocket double gate NCFET [13,14] have been proposed and shown great ability in achieving steep SS [15] introduces a box ferro FDSOI which attaches ferroelectric layer to buried oxide to mitigate the negative differential resistance (NDR) effect. The first principle explanation of the NDR effect is presented, and the element which can influence the characteristic of NCFETs is also investigated in this reference.…”