2021
DOI: 10.1088/1361-6528/ac3bed
|View full text |Cite
|
Sign up to set email alerts
|

Bottom-up nanoscale patterning and selective deposition on silicon nanowires

Abstract: We demonstrate a bottom-up process for programming the deposition of coaxial thin films aligned to the underlying dopant profile of semiconductor nanowires. Our process synergistically combines three distinct methods – vapor-liquid-solid (VLS) nanowire growth, selective coaxial lithography via etching of surfaces (SCALES), and area-selective atomic layer deposition (AS-ALD) – into a cohesive whole. Here, we study ZrO2 on Si nanowires as a model system. Si nanowires are first grown with an axially modulated n-S… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
3

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(1 citation statement)
references
References 43 publications
0
1
0
Order By: Relevance
“…The downscaling of integrated circuits in the semiconductor industry requires extremely accurate deposition and patterning of materials . Feature alignment at the nanometer level during the fabrication of state-of-the-art semiconductor devices has become a bottleneck in the advancement to smaller transistor nodes. As a solution, the use of area-selective deposition (ASD) in self-aligned fabrication schemes is being explored in industry and academia. ASD aims at selective deposition of a material on a patterned substrate, such that growth only occurs on the surfaces where deposition is desired (i.e., the growth area), while the growth is blocked on the rest of the substrate (the non-growth area). As a result, ASD allows for bottom-up and self-aligned deposition with respect to underlying device layers.…”
Section: Introductionmentioning
confidence: 99%
“…The downscaling of integrated circuits in the semiconductor industry requires extremely accurate deposition and patterning of materials . Feature alignment at the nanometer level during the fabrication of state-of-the-art semiconductor devices has become a bottleneck in the advancement to smaller transistor nodes. As a solution, the use of area-selective deposition (ASD) in self-aligned fabrication schemes is being explored in industry and academia. ASD aims at selective deposition of a material on a patterned substrate, such that growth only occurs on the surfaces where deposition is desired (i.e., the growth area), while the growth is blocked on the rest of the substrate (the non-growth area). As a result, ASD allows for bottom-up and self-aligned deposition with respect to underlying device layers.…”
Section: Introductionmentioning
confidence: 99%