Blue Gene/L compute chip: Control, test, and bring-up infrastructure

Abstract

The Blue Genet/L compute (BLC) and Blue Gene/L link (BLL) chips have extensive facilities for control, bring-up, self-test, debug, and nonintrusive performance monitoring built on a serial interface compliant with IEEE Standard 1149.1. Both the BLL and the BLC chips contain a standard eServere chip JTAG controller called the access macro. For BLC, the capabilities of the access macro were extended 1) to accommodate the secondary JTAG controllers built into embedded PowerPC t cores; 2) to provide direct access to memory for initial boot code load and for messaging between the service node and the BLC chip; 3) to provide nonintrusive access to device control registers; and 4) to provide a suite of chip configuration and control registers. The BLC clock tree structure is described. It accommodates both functional requirements and requirements for enabling multiple built-in self-test domains, differentiated both by frequency and functionality. The chip features a debug port that allows observation of critical chip signals at full speed. * Trademark or registered trademark of International Business Machines Corporation.

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

“…Both architectures are designed to scale to 65,536 nodes arranged in a toroidal interconnect which supports both point-to-point and multicast communications and both architectures communicate with a host machine via a subset of nodes which have Ethernet interfaces. However, Blue Gene/L is distinguished by dedicated hardware which translates Ethernet frames into a native control protocol for direct administration of each node in the machine [6]. Conversely, nodes in a SpiNNaker machine which do not have an Ethernet interface may only communicate with the host via the interprocessor communication fabric to the nearest Ethernet-connected node.…”

Overview of the Blue Gene/L system architecture

“…In this section, we briefly explain these networks. Considerably more detail may be found in the papers in this issue dedicated to the BG/L networks [18][19][20]. All network logic is integrated into the BG/L node ASIC.…”

“…The 64Ki-node Blue Gene/L computer contains more than 250,000 endpoints in the form of ASICs, temperature sensors, power supplies, clock trees, fans, status light-emitting diodes, and more, and all must be initialized, controlled, and monitored [20]. These actions are performed by an external commodity computer, called the service node, which is part of the host computer.…”

“…As illustrated in Figure 4(c), the control-FPGA also converts from Ethernet to serial JTAG. As described in [20] and [22] in this issue, JTAG is used for initial program load and debug access to every node, which makes host control of the BG/L nodes very simple and straightforward. JTAG also allows access to the registers of every processor through, for example, the IBM RiscWatch software running on the host.…”

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric

“…The system must somehow break symmetry, assign and load memory resources, configure communications, and start up the processors, while balancing concurrency and resource contention for maximum efficiency. Where previous solutions [4] [5] have typically been using sideband communications or dedicated preconfigured resources, SpiNNaker confronts the challenge of configuring an isotropic undifferentiated parallel processing system headon.…”