Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric

Khan, Muhammad; Rast, Alexander; Navaridas, Javier; Jin, Xin; Plana, Luis A.; Luján, Mikel; Temple, Steve; Patterson, Cameron; Richards, Dominic; Woods, J.V.; Miguel-Alonso, José; Furber, Steve

doi:10.1016/j.parco.2011.02.003

Cited by 4 publications

(1 citation statement)

References 12 publications

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“…The system controller is in charge of performing management functions at the chip level. Finally, every chip has an Ethernet connection that can be used for loading the application data [11], managing the system from a console and also for fault-tolerance purposes. However, given that this sub-module requires a dedicated core, only a few chips of the system will make use of this connection, being them in charge of distributing through the SpiNNaker interconnection network the necessary Ethernet received traffic.…”

Section: Spinnaker Nodementioning

confidence: 99%

SpiNNaker

Navaridas

Plana

Miguel-Alonso

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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The SpiNNaker system is a biologically-inspired massively parallel architecture of bespoke multi-core System-on-Chips. The aim of its design is to simulate up to a billion spiking neurons in (biological) real-time. Packets, in SpiNNaker, represent neural spikes and these travel through the two-dimensional triangular torus network that connects the over 65 thousand nodes housed in the largest size of SpiNNaker.The research question that we explore is the impact that spatial locality, temporal causality and burstiness of the traffic have on the performance of such interconnection network. Given the limited knowledge of neuron activity patterns, we propose and use synthetic traffic patterns which resemble biological neural traffic and allow tuning of spatial locality. Causality is explored by means of temporal patterns that maintain a specified overall network load while allowing at the node level autonomous causal traffic generation. Part of the traffic is generated automatically, but the remaining traffic is triggered by a spike arrival in the form of a packet or a burst of packets; as neural stimuli do. In this way, we generate non-uniform traffic patterns with an evolving concentration of activity at nodes which contain more active parts of the spiking neural network.Given the application domain, the simulation-based study focuses on the real-time behavior of the system rather than focusing on standard HPC network metrics. The results show that the interconnection network of SpiNNaker can operate without dropping packets with traffic loads that exceed more than 3.5 times those required to simulate 10 9 spiking neurons, despite using nonlocal traffic. We also find that increments in the degree of traffic causality do not affect the performance of the system, but burstiness in the traffic can hurt performance. SpiNNaker is a system-on-chip (SoC)-based architecture designed to support the real-time simulation of large networks of spiking neurons (up to 10 9 ). To emulate the very high connectivity of biological systems, SpiNNaker uses a self-timed, packet-switched interconnection network which gives support to efficient multicast, with high bandwidth and low-delay. The heart of the communication infrastructure is an on-chip router and the self-timed implementation of the fabric that allows the seamless extension of the on-chip communications to include the inter-chip links. We encourage the interested reader to check [15] for a more detailed description of the system at hardware level and [7] for an engineering-oriented overview of biologically plausible neural networks applications and systems.

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Section: Spinnaker Nodementioning

confidence: 99%

SpiNNaker

Navaridas

Plana

Miguel-Alonso

et al. 2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture

Navaridas¹,

Furber²,

Garside³

et al. 2013

Parallel Computing

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Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

Sharp

Patterson

Furber

2011

The 2011 International Joint Conference on Neural Networks

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Abstract-SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 2 16 homogeneous eighteencore multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms.

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Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric

Cited by 4 publications

References 12 publications

SpiNNaker

SpiNNaker

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

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