Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

Abstract

Abstract-SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 2 16 homogeneous eighteencore multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms.

Scalable communications for a million-core neural processing architecture

“…Experiments on SpiNNaker hardware using this self-propagating technique yielded results shown in Fig. 11a, further detailed in [50]. The times, as expected, proved linear to the number of hops, and the duration of the system boot phase for any regular topology can be anticipated (Fig.…”

SpiNNaker - programming model

“…The overall process is a self-timed pipeline, and the completion time is a function of the system size. As a reference point, it takes around 1 second on an 864 core system; quantitative timing data is available in [4]. As with the previous step, it is not possible for any one point in the system to know when the overall process has terminated, so this step is also timed out by the Uploader.…”

“…The hardware architecture of the machine is described in detail elsewhere [1], [2], [3], [4], [16]-here we describe the low-level software infrastructure necessary to underpin the operation of the machine. It is tempting to call this an operating system, but we have resisted this label because the term induces preconceptions, and the architecture and mode of operation of the machine does not provide or utilise resources conventionally supported by an operating system.…”

VLSI circuits implementing computational models of neocortical circuits

“…This idea has been known as "neuromorphic engineering" (Mead, 1989), although the term has been lately applied to many specialised digital architectures as well (Sharp et al, 2011;Merolla et al, 2011). In practice, most of the neuromorphic systems are mixed-mode implementations that combine the analogue circuit implementations of model equations and digital event-based read-out (Boahen, 2000) and spike routing sub-system (Lin et al, 2006;Vogelstein et al, 2007;Serrano-Gotarredona et al, 2009;Schemmel et al, 2010).…”

“…Recently, a number of systems have been proposed (Arthur and Boahen, 2004;Vogelstein et al, 2007;Merolla et al, 2007Merolla et al, , 2011Giulioni et al, 2008;Schemmel et al, 2010;Sharp et al, 2011) that attempt to facilitate the implementation of large-scale hardware neural networks, through the integration of thousands of silicon neurons and synapses in a single microelectronic IC.…”