Block-level 3D IC design with through-silicon-via planning

Kim, Dae Hyun; Topaloglu, Rasit Onur; Lim, Sung Kyu

doi:10.1109/aspdac.2012.6164969

Cited by 28 publications

(12 citation statements)

References 10 publications

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“…This increase is mainly due to longer interconnects passing multiple dies (notably caused by nets connecting to external pins), which undermines wirelength reduction by shorter inter-die routes. Depending on die thickness, inserting multiple TSVs guided by tree construction may reduce wirelength [19]. However, this would increase TSV count notably and thus cost as well.…”

Section: Experimental Results Inmentioning

confidence: 99%

“…Our optimization methodology MoDo is presented in Section III; an experimental investigation is provided in Section IV. Our conclusions on optimizing deadspace for 3D ICs and its benefits are given in Section V. [25]) [19], [20] rarely aligned nonuniform; Thermal ≈ 2 − 40µm may be encouraged low -medium irregular small -medium contigous regions; [7] [8], [9], [27] possibly aligned nonuniform; Power/Ground ≈ 10 − 40µm strongly preferred low irregular small contigous regions; [7], [13], [14], [16] [11], [13], [14], [16] necessarily aligned nonuniform; Clock ≈ 2 − 20µm may be encouraged low irregular small contigous regions; [33] [33], [34] possibly aligned…”

Section: Introductionmentioning

confidence: 99%

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Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

Knechtel

Markov

Lienig

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-In 3D-IC integration and its implied resource optimization, a particularly critical resource is deadspace -regions between floorplan blocks. Deadspace is required for through-silicon via (TSV) planning and other related design tasks, but the effective use of this limited and highlycontested resource requires effort. While most previous work focuses on a single design issue at a time, we propose a lightweight multiobjective deadspace-optimization methodology that simultaneously optimizes interconnect, IR-drop, clock-tree size and maximal temperature. This methodology repeatedly re-evaluates design quality during early chip planning and uses resulting information to guide further optimization. Experimental results indicate that constructing an appropriate deadspace distribution improves design tradeoffs and is effective in practice.

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Section: Experimental Results Inmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

Knechtel

Markov

Lienig

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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“…As the table shows, the maximum difference is 12.1%, but the average difference for the arithmetic circuits (AL1-AL7) is −3.6% and that for the microprocessor circuits (MP1-MP5) is −3.0%. 2 Table II compares the wirelength of the layouts of the four benchmark circuits designed by [21] and the wirelength predicted by our TSV-aware block-level 3-D wirelength distribution model. The maximum difference is 9.0% and the average difference is 3.1%, which are acceptable as a prediction result in early design stages.…”

Section: B Validation Of the Tsv-aware 3-d Wirelength Distribution Mmentioning

confidence: 99%

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

Kim

Mukhopadhyay

Lim

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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3-D integrated circuits (3-D ICs) are expected to have shorter wirelength, better performance, and less power consumption than 2-D ICs. These benefits come from die stacking and use of through-silicon vias (TSVs) fabricated for interconnections across dies. However, the use of TSVs has several negative impacts such as area and capacitance overhead. To predict the quality of 3-D ICs more accurately, TSV-aware 3-D wirelength distribution models considering the negative impacts were developed. In this paper, we apply an optimal buffer insertion algorithm to the TSV-aware 3-D wirelength distribution models and present various prediction results on wirelength, delay, and power consumption of 3-D ICs. We also apply the framework to 2-D and 3-D ICs built with various combinations of process and TSV technologies and predict the quality of today and future 3-D ICs. Index Terms-3-D IC, interconnect prediction, through-silicon via (TSV), wirelength distribution.

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“…A typical example is core + memory stack [7], which provides very high memory access bandwidth. The second one is block-level integration [8], where functional blocks are partitioned into different tiers based on their logical connections. In block-level integration, the number of vertical connections is usually more than core + memory stacking.…”

Section: Benefits Of Monolithic 3d For 3d Integrationmentioning

confidence: 99%

A design tradeoff study with monolithic 3D integration

Liu

Lim

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-This paper studies various design tradeoffs existing in the monolithic3Dintegrationtechnology.Differentdesignstylesinmonolithic 3D ICs are studied, including transistor-level monolithic integration (MI-TR) and gate-level integration (MI-G). GDSII-level layout of monolithic 3D designs are constructed and analyzed. Compared with its 2D counterparts, MI-TR designs have advantages in footprint area, wire-length, timing, and power, because of the smaller footprint. MI-G design style also demonstrate advantages in area, timing and power over TSV-based designs, because of the smaller size and parasitics of inter-tier vias compared with TSVs. To further take the advantage of monolithic 3D technology, several technology improvement options are also explored. Besides, some possible design challenges with monolithic 3D are also studied, including global variation and signal integrity issues.

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Block-level 3D IC design with through-silicon-via planning

Cited by 28 publications

References 10 publications

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

A design tradeoff study with monolithic 3D integration

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