BIST-based diagnostics of FPGA logic blocks

Stroud, Charles E.; Lee, E.; Abramovici, M.

doi:10.1109/test.1997.639662

Cited by 77 publications

(43 citation statements)

References 17 publications

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“…Therefore, while these tests can be used for manufacturing test, they are not applicable to insystem test or to fault-tolerant system applications. In contrast, BIST-based methods [37] [38][39] [7] [40] hence its resolution requirement is only to identify a faulty row (or column). When the goal of testing is the improvement of the manufacturing process, then the most accurate resolution -locating faults inside a PLB -is required to support subsequent failure analysis.…”

Section: Introductionmentioning

confidence: 99%

BIST-based test and diagnosis of FPGA logic blocks

Abramovici¹,

Stroud

2001

IEEE Trans. VLSI Syst.

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100

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We present a Built-In Self-Test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers, that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

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Section: Introductionmentioning

confidence: 99%

BIST-based test and diagnosis of FPGA logic blocks

Abramovici¹,

Stroud

2001

IEEE Trans. VLSI Syst.

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100

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“…Reliable devices together with fault-tolerance and test strategies are used in order to accomplish this target. In the past few years, strategies to improve the dependability features of reconfigurable computer systems, have been proposed and implemented [1,[7][8][9][10][11][12]. These strategies are mainly based on the traditional ones used in microprocessor based systems.…”

Section: Introductionmentioning

confidence: 99%

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Bezerra

Vargas

Gough

2001

Journal of Electronic Testing

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Abstract. This paper revises and introduces to the field of reconfigurable computer systems, some traditional techniques used in the fields of fault-tolerance and testing of digital circuits. The target area is that of on-board spacecraft electronics, as this class of application is a good candidate for the use of reconfigurable computing technology. Fault tolerant strategies are used in order for the system to adapt itself to the severe conditions found in space. In addition, the paper describes some problems and possible solutions for the use of reconfigurable components, based on programmable logic, in space applications.

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“…Off-line testing methods for FPGAs are reasonably mature and well developed [8,9,15]. Offline testing is acceptable in application environments where there are little real-time or time-to-market constraints on the device or system being tested.…”

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confidence: 99%

Efficient on-line testing of FPGAs with provable diagnosabilities

Verma

Dutt

Suthar

2004

Proceedings of the 41st Annual Design Automation Conference

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We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1-and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE, and that avoid expensive adaptive diagnosis. To the best of our knowledge, this is the first time that a BISTer design with diagnosability greater than one has been developed for FPGAs. We also develop functional testing methods that test PLBs in only two circuit functions that will be mapped to them (as opposed to testing PLBs in all their operational modes) as the ROTE moves across a functioning FPGA. Simulation results show that our 1-diagnosable BISTer and our functional testing technique leads to significantly more accurate (98% (90.5%) fault coverage at a fault/defect density of 10% (25%)) and faster test-and-diagnosis of FPGAs than achieved by previous work. In general, it is expected that ROTE will achieve high fault coverages at fault/defect densities of up to 25% using our 1-diagnosable BISTer and up to 33% using our 2-diagnosable BISTer. Our methods should thus prove useful for testing current very deep submicron FPGAs as well as future nano-CMOS and molecular nanotechnology FPGAs in which defect densities are expected to be in the 10% range.

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BIST-based diagnostics of FPGA logic blocks

Cited by 77 publications

References 17 publications

BIST-based test and diagnosis of FPGA logic blocks

BIST-based test and diagnosis of FPGA logic blocks

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Efficient on-line testing of FPGAs with provable diagnosabilities

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