Bias dependence of TID radiation responses of 0.13μm partially depleted SOI NMOSFETs

Ning, Bingxu; Bi, Dawei; Huang, Huixiang; Zhang, Zhengxuan; Hu, Zhiyuan; Chen, Ming; Zou, Shichang

doi:10.1016/j.microrel.2012.08.005

Cited by 28 publications

(10 citation statements)

References 17 publications

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“…Interestingly, the 0V-F bias has similar shift value with the ON-F case, which demonstrates that the charge trapping in BOX is not influenced by the gate bias during irradiation [10,12]. As expected, the PG bias condition, the worst irradiation bias for back channel [10,12,17], introduces much larger negative threshold voltage shift than that of ON bias. However, different from the ON case group, there is no significant difference between the PG bias and PG-F bias.…”

Section: Methodssupporting

confidence: 66%

“…However, the thick buried oxide (BOX) layer threatens the reliability of SOI devices during ionizing radiation, in which the positive trapped charges will build up in the BOX after total ionizing dose, reducing the threshold voltage of back-gate transistor and increasing leakage current [6,7,8,9]. The radiation response of buried oxides has been found to be highly dependent on the device bias configuration during radiation, which determines the electrical field distribution in BOX [10,11,12,13,14,15,16,17,18].…”

Section: Introductionmentioning

confidence: 99%

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Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET

Zhu

Xie

et al. 2020

IEICE Electron. Express

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The total-ionizing-dose response of partially-depleted siliconon-insulator devices with or without grounded substrate under different irradiation bias is investigated. Compared with devices with grounded substrate, the devices with floating substrate introduces more trapped positive charges in buried oxide after irradiation, leading to larger negative shift of back-gate threshold voltage, especially for ON bias condition. Theoretical analysis and TCAD simulation demonstrate that, this phenomenon is attributed to the increased initial built-in field in buried oxide and weakened space charge effect under the case of floating substrate. According to this work, substrate terminal of SOI devices must be considered for integrated circuit design under radiation condition.

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Section: Methodssupporting

confidence: 66%

Section: Introductionmentioning

confidence: 99%

Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET

Zhu

Xie

et al. 2020

IEICE Electron. Express

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“…The capacitance-voltage (CV) method has difficulty in measuring accurately interface trap density in deep submicron transistors. The characterization of back interface properties in SOI transistors remains a challenge [13], [14]. The direct-current current-voltage (DCIV) technique proposed by Sah and Jie in 1995 [15] has been employed for the measurement of back-channel interface traps in SOI devices [16], [17].…”

Section: Introductionmentioning

confidence: 99%

Effect of Radiation on Interface Traps of SOI NMOSFETs by the Direct-Current Current-Voltage Technique

et al. 2019

IEEE Access

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This paper investigates the effect of total ionizing dose radiation on back-gate interface traps in SOI NMOSFETs. The concentration and energy distribution of interface traps at Si/SiO 2 back-gate interface of SOI NMOSFETs during irradiation are studied by the direct-current current-voltage technique. When transistors are subjected to radiation, DCIV bulk current increases. The calculated results suggest that the interface trap density increases and its equivalent energy level is far away from the midgap with irradiation dose increasing, which can be explained by the energy distribution of interface traps. The interface trap energy density D IT (E IT ) as a function of the energy level E IT has been obtained by the least square optimization and shows the typical ''U-shape'' distribution. In detail, the rising humps at equivalent energy level in D IT (E IT ) curves are due to Si-H bonds that are broken down after irradiation, which corresponds to the increasing trap density. Moreover, it is found that the energy level of interface traps is redistributed after irradiation. The peak of humps in D IT (E IT ) curves occurs at the farther energy level with the increase of dose, which is similar to the equivalent energy level. It might arise from the shallow energy level of interface traps induced by radiation.INDEX TERMS SOI, interface traps, radiation, energy distribution.

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“…1(b) [24], [25]. However, further examination shows that the high body doping used in this device makes it immune to the formation of a leakage path up to very high total doses, and furthermore, that there exists a threshold above which no further charges are being trapped due to an equivalent positive charge density aggregating at the bottom of the BOX [17].…”

Section: Silicon-on-insulator and Shallow Trench Isolationmentioning

confidence: 98%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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Bias dependence of TID radiation responses of 0.13μm partially depleted SOI NMOSFETs

Cited by 28 publications

References 17 publications

Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET

Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET

Effect of Radiation on Interface Traps of SOI NMOSFETs by the Direct-Current Current-Voltage Technique

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

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