Bias and geometry optimization of FinFET for RF stability performance

Sivasankaran, K.; Mallick, P. S.

doi:10.1007/s10825-013-0507-2

Cited by 13 publications

(13 citation statements)

References 15 publications

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“…Scaling of channel length and contact length of the device to as low as 15 and 20 nm, respectively, was found to be feasible without any short channel effects (SCE) and drain induced barrier lowering (DIBL) effects. Further, the drain current I d for 15, 300 and 3 μm channel lengths is around 5, 3, and 1.5 μA, respectively, for an input voltage of 0.25 V [18]. The relation between the channel length and the total resistance, R tot of the device can be given as…”

Section: Transistor Sizing For Sub-threshold Operationmentioning

confidence: 99%

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High‐speed sub‐threshold operation of carbon nanotube interconnects

Sathyakam¹,

Mallick²,

Saxena³

2019

IET Circuits, Devices & Systems

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Sub-threshold voltage operated circuits are the future for ultra-low-power applications. These circuits are inherently slow due to the very small sub-threshold currents. Here, the authors propose two approaches for improving the speed of SWCNT bundle interconnects driven by CNTFET-based circuits under sub-threshold conditions. First, the authors modulate the channel length of the CNTFETs that are used in the driver circuits to increase sub-threshold output current. The output current is maximum when the channel length is optimised to 15 nm. Second, the authors design driver circuits made of CNTFET-based inverters and transmission gates for SWCNT bundle interconnects at sub-threshold voltages. The authors consider five different configurations of the driver and load circuits. SPICE simulations show that transmission gates play a vital role in driver circuits by reducing the propagation delay and increasing the switching speed at high frequencies. Finally, the authors perform temperature-dependent analysis of the best cases from the proposed circuits and show that the propagation delay and power dissipated by them increases drastically at increased temperatures up to 500 K. 2 CNTFET current model CNTFET is regarded as the most advanced device which has similarities of MOSFET but has an advantage of working in

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Section: Transistor Sizing For Sub-threshold Operationmentioning

confidence: 99%

“…High speed operation and low-power consumption in scaled down circuits at sub-threshold region can be achieved by using nanoscale transistors like FinFETs [18], CNTFETs [19][20][21], or GNRFETs connected by CNT interconnects.…”

Section: Introductionmentioning

confidence: 99%

High‐speed sub‐threshold operation of carbon nanotube interconnects

Sathyakam¹,

Mallick²,

Saxena³

2019

IET Circuits, Devices & Systems

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“…The objective of this study is to optimize the parasitic capacitance at the device level itself so that transistor has better stability and does not require any additional stabilization network. For multigate transistors, the RF stability model was developed and parasitic optimization has been presented and also provided design guidelines for improving the maximum stable gain (MSG), maximum power gain, f max , and f T . Impact of variation physical parameters on the analog performance of the multigate is studied.…”

Section: Introductionmentioning

confidence: 99%

“…For multigate transistors, the RF stability model was developed and parasitic optimization has been presented and also provided design guidelines for improving the maximum stable gain (MSG), maximum power gain, f max , and f T . [18][19][20] Impact of variation physical parameters on the analog performance of the multigate is studied. In the present work, we have investigated the impact of dielectric spacers and the length of the dielectric spacer on the parameters associated with RF stability of the double gate junctionless transistor (DGJLT) device.…”

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confidence: 99%

Impact of high k spacer on RF stability performance of double gate junctionless transistor

Raju

Sivasankaran

2018

Int J Numerical Modelling

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In this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut-off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability. KEYWORDS double gate junctionless transistor (DGJLT), high k spacer, MAG, MSG, RF stability, unity gain cutoff frequency 1 | INTRODUCTIONAccording to the International Technology Roadmap for Semiconductors, alternative metal-oxide-semiconductor field-effect transistor (MOSFET) structures serve the need for devices beyond 16 nm. 1 One of the promising devices which can substitute the conventional MOSFET is junctionless transistor (JLT). 2 Junctionless transistor does not have PN junctions because source, channel, and drain are of same doping, which overcomes the problems associated with doping profile of MOSFETs. It also offers many advantages over conventional bulk MOSFETs such as better scalability, reduced short channel effects, simple fabrication process flow, and low thermal budgets after gate formation. [3][4][5] The JLT has received attention for analog/radio frequency (RF) applications due to its improved intrinsic gain and maximum oscillation frequency ( f max ). 6 Many works were carried on JLTs about enhancing the electrostatic integrity using a high k spacer, drain/source extension, and gate work function on analog and RF applications. 7-12 Impact of process parameter variation on the analog and RF performance of the multigate is studied. 13 The RF model was developed to extract the parameters like cut-off frequency ( f T ), input capacitance, and distribute channel resistance of junctionless silicon nanowire MOSFET. 14 The quantum mechanical model of gate all around nanowire MOSFET is developed to examine the effect of high k gate dielectric on the electrostatics and device performance. 15 The reliability issues of graded channel junctionless multigate transistor in analog performance are investigated. 16 From the literature review, we found that many studies were carried on analog and RF performance of JLTs. However, RF stability study on JLTs is not reported, which is an important figure of merit for the design of RF amplifiers or

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“…Stability is one of the important parameter in RF amplifier design which requires attention. Some works were carried on RF stability performance on DG-MOSFET, Silicon Nanowire Transistor, and FinFET [9][10][11]. In this work RF stability performance of JLTGT was studied which is an important parameter in Radio Frequency integrated circuit design (RFIC).…”

Section: Introductionmentioning

confidence: 99%

Impact of bias, doping and High-K dielectric on RF stability performance of junctionless tri-gate transistor

Vyas

Deshpande

Sharma

et al. 2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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This paper presents the effect of process parameter variation such as oxide material, oxide thickness, doping concentration along with bias conditions and different high-k dielectric on RF stability performance of Junctionless Tri-Gate Transistor (JLTGT). The small signal RF parameter is obtained from extracted device parameters using TCAD (Technology Computer Aided Design). The results show that optimized JLTGT shows good RF stability performance.

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Bias and geometry optimization of FinFET for RF stability performance

Cited by 13 publications

References 15 publications

High‐speed sub‐threshold operation of carbon nanotube interconnects

High‐speed sub‐threshold operation of carbon nanotube interconnects

Impact of high k spacer on RF stability performance of double gate junctionless transistor

Impact of bias, doping and High-K dielectric on RF stability performance of junctionless tri-gate transistor

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