High‐speed sub‐threshold operation of carbon nanotube interconnects

Sathyakam, P. Uma; Mallick, P. S.; Saxena, Anmol Ajay

doi:10.1049/iet-cds.2018.5118

Cited by 11 publications

(5 citation statements)

References 35 publications

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“…Further discussions and models of phonon scattering in CNT interconnects can be found here. 27 The temperature profile of the interconnects depicted in Fig. 3c inset looks similar for both S-CNT and T-CNT interconnects.…”

Section: Proposed Fabrication Steps Of T-cnt Bundle Interconnectsmentioning

confidence: 76%

Perspective—Demystifying the Power Withstanding Capabilities of CNT Bundle Interconnects

Robert

Sathyakam

2022

ECS J. Solid State Sci. Technol.

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This article discusses power consumption trends of two geometries of carbon nanotube (CNT) bundle interconnects for very large scale integration applications. Electrostatic and electrothermal field simulations of square and triangular CNT bundle interconnects were done. Two factors viz. power dissipated and peak temperature are extracted and a new figure of merit called power temperature product (PTP) is defined. The PTP is calculated for interconnect lengths ranging from 500 to 2000µm. Results show that both triangular and square CNT bundles have high power withstanding capacity. Triangular CNT bundles have higher PTP when the associate phase changes are ignored.

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Section: Proposed Fabrication Steps Of T-cnt Bundle Interconnectsmentioning

confidence: 76%

Perspective—Demystifying the Power Withstanding Capabilities of CNT Bundle Interconnects

Robert

Sathyakam

2022

ECS J. Solid State Sci. Technol.

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“…These transistors can also exhibit ballistic transport of charge carriers between the source and drain terminals at higher speeds [34][35][36][37]. In other words, CNTFETs can have the similar physical structure as the MOSFETs, but with the only difference that in CNTFET the carbon nanotubes (CNT) between the drain and source terminals act as the conducting channels [38].…”

Section: A Brief Review On Carbon Nanotube Field Effect Transistor Te...mentioning

confidence: 99%

“…As reported in [38], the major advantage of the CNTFETs is their threshold voltage tunability. The threshold voltage of a CNTFET is inversely related to the diameter of the nanotube as it is given in Equation ().…”

Section: A Brief Review On Carbon Nanotube Field Effect Transistor Te...mentioning

confidence: 99%

“…where, W min is the minimum gate width, N is the number of nanotubes, pitch is the distance between the two adjacent nanotube centres, and DCNT is the nanotube diameter [31,32]. As reported in [38], the major advantage of the CNTFETs is their threshold voltage tunability. The threshold voltage of a CNTFET is inversely related to the diameter of the nanotube as it is given in Equation (3).…”

Section: A Brief Review On Carbon Nanotube Field Effect Transistor Te...mentioning

confidence: 99%

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An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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“…Although an increase in resistivity primarily responsible for higher resistance of metallic interconnect and becomes encumbrance due to hillock formation, surface, and grain boundary scattering [1]. Besides, the crosstalk‐induced delay becomes the bottleneck for advanced technology due to the closer proximity of wires and higher interconnect density [2]. For higher interconnect lengths, the per unit length (p.u.l.)…”

Section: Introductionmentioning

confidence: 99%