Benchmarking data analysis and machine learning applications on the Intel KNL many-core processor

Byun, Chansup; Kepner, Jeremy; Arcand, William; Bestor, David; Bergeron, Bill; Gadepally, Vijay; Houle, Michael E.; Hubbell, Matthew; Jones, Michael; Klein, Anna; Michaleas, Peter; Milechin, Lauren; Mullen, Julie; Prout, Andrew; Rosa, Antonio; Samsi, Siddharth; Yee, Charles; Reuther, Albert

doi:10.1109/hpec.2017.8091067

Cited by 13 publications

(8 citation statements)

References 21 publications

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“…Several papers have explored the performance of the KNL architecture, mainly through the analysis of well-known benchmarks, machine learning applications, and parallel workloads [1,2,4,8]. None of these works undertake the analysis of the locality characteristics of the KNL interconnect.…”

Section: Related Workmentioning

confidence: 99%

Effect of Distributed Directories in Mesh Interconnects

MarcosHorro

Kandemir

Pouchet

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Xeon Phi Knights Landing. It features 38 tiles packed in a single die, organized into a 2D mesh. Before accessing remote data, tiles need to query the distributed directory. The effect of this coherence traffic is poorly understood. We show that the apparent UMA behavior results from the degradation of the peak performance. We develop ways to optimize the coherence traffic, the core-to-core-affinity, and the scheduling of a set of tasks on the mesh, leveraging the unique characteristics of processor units stemming from process variations.

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Section: Related Workmentioning

confidence: 99%

Effect of Distributed Directories in Mesh Interconnects

MarcosHorro

Kandemir

Pouchet

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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“…As suggested by the technical report [5] regarding KNL's cluster modes, users avoided to use KNL as a UMA system. Byun et al [15] evaluated performance of data-analysis and machine-learning applications on KNL. For the experiments, they avoided to use KNL as a UMA cache (with allto-all cluster mode) system.…”

Section: Background and Motivations A Use Cases On Knlmentioning

confidence: 99%

Analysis of Memory System of Tiled Many-Core Processors

2019

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Tiled many-core processors are designed to integrate simple cores onto a single chip to take advantage of software-level parallelism, and these cores are interconnected via mesh-based networks to mitigate overheads such as limited throughput derived from traditional interconnects. As these processors become more prevalent, one unnoticed problem is that it is more likely for operating system (OS) designers to believe that these processors, which have multiple on-chip memory controllers, belong to the non-uniform memory access (NUMA) system. In this paper, we define novel models regarding the differentiation between uniform memory access and NUMA on tiled many-core processors from the perspective of the cache system to facilitate OS designers and application programmers in fully understanding the underlying hardware. Whether or not a tiled many-core processor belongs to the NUMA system, is determined by the cache system rather than how many memory controllers it has. The experimental results together with the novel models are able to explain why the (non-)significant performance difference can be observed on KNL and TILE-Gx72.

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“…Several recent papers have explored the performance of the Knights Landing architecture, mainly through the analysis of well-known benchmarks, machine learning applications, and parallel workloads [24]- [26]. This type of works analyze the scalability of the processor and provide the observed trends in terms of performance of real workloads, which are then compared against the theoretical performance.…”

Section: Related Workmentioning

confidence: 99%

Simulating the Network Activity of Modern Manycores

2019

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Manycore architectures are one of the most promising candidates to reach the exascale. However, the increase in the number of cores on a single die exacerbates the memory wall problem. Modern manycore architectures integrate increasingly complex and heterogeneous memory systems to work around the memory bottleneck while increasing computational power. The Intel Mesh Interconnect architecture is the latest interconnect designed by Intel for its HPC product lines. Processors are organized in a rectangular network-on-chip (NoC), connected to several different memory interfaces, and using a distributed directory to guarantee coherent memory accesses. Since the traffic on the NoC is completely opaque to the programmer, simulation tools are needed to understand the performance trade-offs of code optimizations. Recently featured in Intel's Xeon Scalable lines, this interconnect was first included in the Knights Landing (KNL), a manycore processor with up to 72 cores. This work analyzes the behavior of the Intel Mesh Interconnect through the KNL architecture, proposing ways to discover the physical layout of its logical components. We have designed and developed an extension to the Tejas memory system simulator to replicate and study the low-level data traffic of the processor network. The reliability and accuracy of the proposed simulator is assessed using several state-of-the-art sequential and parallel benchmarks, and a particular Intel Mesh Interconnect-focused locality optimization is proposed and studied using the simulator and a real KNL system.

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Benchmarking data analysis and machine learning applications on the Intel KNL many-core processor

Cited by 13 publications

References 21 publications

Effect of Distributed Directories in Mesh Interconnects

Effect of Distributed Directories in Mesh Interconnects

Analysis of Memory System of Tiled Many-Core Processors

Simulating the Network Activity of Modern Manycores

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