Analysis of Memory System of Tiled Many-Core Processors

Abstract

Tiled many-core processors are designed to integrate simple cores onto a single chip to take advantage of software-level parallelism, and these cores are interconnected via mesh-based networks to mitigate overheads such as limited throughput derived from traditional interconnects. As these processors become more prevalent, one unnoticed problem is that it is more likely for operating system (OS) designers to believe that these processors, which have multiple on-chip memory controllers, belong to the non-uniform memory access (NUMA) system. In this paper, we define novel models regarding the differentiation between uniform memory access and NUMA on tiled many-core processors from the perspective of the cache system to facilitate OS designers and application programmers in fully understanding the underlying hardware. Whether or not a tiled many-core processor belongs to the NUMA system, is determined by the cache system rather than how many memory controllers it has. The experimental results together with the novel models are able to explain why the (non-)significant performance difference can be observed on KNL and TILE-Gx72.

Optimization of the Load Balancing Policy for Tiled Many-Core Processors

“…The difference in the scalability problem between KNL and the TILE-Gx72 processor is associated with the memory (cache) system of the tiled many-core processor, even though they have common features (i.e., tiles are fitted onto a single chip) as discussed in Section II-C. As analyzed in our previous work [39], on the NUMA mode, a quarter of the whole L2 caches (with in total 8-MB instead of 32-MB capacity) on KNL can be used as LLC (multiple virtual LLCs coexist on KNL) to store any memory block, whereas on the TILE-Gx72 processor, the whole L2 caches (with 18-MB capacity) are viewed as LLC. It is well-studied that program performance is dominated by the CPU time allocated to threads, the cache capacity that guarantees data can be found to support the thread execution, and communication between threads for HPC applications.…”

“…OS designers, whose work is planned to move from traditional multicore (many-core) systems to emerging tiled many-core processors, first need to fully understand what the memory (cache) system on a given tiled many-core processor is. For instance, as stated in our work [39], with the NUMA mode, any memory block is allowed to be stored on a quarter of the area of the total L2 caches when KNL is configured with SNC-4 cluster mode and flat cache mode, whereas on the TILE-Gx72 processor, it can be present on the whole L2 caches. Misunderstanding that risks causing unnoticed and difficult-to-detect bottlenecks on the OS.…”

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

“…In addition, our proposed cache system solution may also provide the ability to increase the cache levels and sizes within the cache hierarchy upon cache reconfiguration in order to optimize the system for cost, performance and power consumption. Some earlier research [13]- [16] have addressed various cache system architecture, issues and solutions for improved performance. In [13], the authors addressed analyzing memory performance for tiled many-core CMP.…”

“…Some earlier research [13]- [16] have addressed various cache system architecture, issues and solutions for improved performance. In [13], the authors addressed analyzing memory performance for tiled many-core CMP. Lin et al [14] suggested hybrid cache systems that included layers for cache architecture from memory to data base to improve performance in specific relational data base query for big data applications.…”

“…Safayenikoo et al [16] suggested an energy-efficient cache architecture to address the problem of increased leakage power resulting from large area of LLC (as much as 50% of the chip area) due to its increased size. Most of the work reported in [13]- [16] may require complex cache design process. Our proposed cache system solution is simple and do not add any extra or difficult cache design process.…”