Simulating the Network Activity of Modern Manycores

Abstract

Manycore architectures are one of the most promising candidates to reach the exascale. However, the increase in the number of cores on a single die exacerbates the memory wall problem. Modern manycore architectures integrate increasingly complex and heterogeneous memory systems to work around the memory bottleneck while increasing computational power. The Intel Mesh Interconnect architecture is the latest interconnect designed by Intel for its HPC product lines. Processors are organized in a rectangular network-on-chip (NoC), connected to several different memory interfaces, and using a distributed directory to guarantee coherent memory accesses. Since the traffic on the NoC is completely opaque to the programmer, simulation tools are needed to understand the performance trade-offs of code optimizations. Recently featured in Intel's Xeon Scalable lines, this interconnect was first included in the Knights Landing (KNL), a manycore processor with up to 72 cores. This work analyzes the behavior of the Intel Mesh Interconnect through the KNL architecture, proposing ways to discover the physical layout of its logical components. We have designed and developed an extension to the Tejas memory system simulator to replicate and study the low-level data traffic of the processor network. The reliability and accuracy of the proposed simulator is assessed using several state-of-the-art sequential and parallel benchmarks, and a particular Intel Mesh Interconnect-focused locality optimization is proposed and studied using the simulator and a real KNL system.

Coherence Traffic in Manycore Processors with Opaque Distributed Directories

“…Going forward, it would be desirable to improve this design, coupling the directory distribution that avoids bottlenecks in the NoC with a more regular and predictable mapping of the memory blocks to enable programmers, particularly in the high-performance computing domain, to have full control over coherence traffic. Horro et al [13] developed a simulator for the traffic on the NoC of distributed directory architectures based on the Tejas architectural simulator [25], predicting that codes with coherence traffic control would experiment a 20% decrease in overall traffic over the NoC, yielding more than 50% latency improvement for the coherence packets.…”

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

“…On-chip networks, also known as networks on chip (NoCs), typically consist of a set of routers that connect to each other and to endpoints in a manner defined by the topology [33]. NoCs have been commercially adopted [34], [35] and may use deterministic, oblivious, or adaptive routing. Moreover, the flow control defines how packets progress through the network.…”

Ring-mesh: a scalable and high-performance approach for manycore accelerators

“…Interestingly, a ring topology can outperform mesh topology for workloads exhibiting moderate to high memory locality accesses [46]. Rings also have been used in commercial systems (e.g., the first generation of Intel Xeon Phi co-processor uses a dual ring topology, while second generation, as well as Intel SkyLake-SP Xeon processor, use a ring-based mesh [22,24,51]). The main advantage of using the ring topology is the low latency offered to the data packets to reach their destinations.…”