Behaviour of TFMS and CPW line on SOI substrate versus high temperature for RF applications

A low-loss V-groove coplanar waveguide on an SOI substrate

“…In Ref. [9], the behavior of a 50-Ω thin film microstrip and a coplanar waveguide (CPW) on SOI substrates at high temperatures were researched.…”

Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology

“…We note a degradation of Q when the temperature varies from 25 to 200°C () up than 30% for the all inductors except the case of the inductor implemented on STD resistivity substrate: the substrate resistivity increases with the temperature rise thanks to the mobility degradation of free carries inside the Si-substrate [20] which compensates the metallic losses and thus minimizing the degradation of STD quality factor with respect to temperature. The inductor implemented on STD with PGS structures (STD-PGS) does not take benifit from the substrate resistivity increase when temperature raises because those inductors are isolated from the silicon substrate and thus not affected by the substrate effects ( Table 3).…”

Nonlinear Properties of Si Based Substrates for Wireless Systems and SoC Integration

“…Added to their simple fabrication process, coplanar structures enable using wider lines to achieve the same characteristic impedance than microstrip structures which leads to reduced metallic losses (9). Besides, in the case of HR SOI, they fully benefit of the high-resistivity properties of the handle substrate, allowing the use of the whole back-end-of-line of the semiconductor process (10).…”