Behavioral synthesis methodology for HDL-based specification and validation

Knapp, David; Ly, Tai; MacMillen, Don; Miller, Robert H.

doi:10.1145/217474.217543

Cited by 36 publications

(14 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Of particular interest within the context of this work are [8] and [21]. In [8], a methodology for HDL-based specification is proposed which has been adopted in the Synopsys Behavioral Compiler.…”

Section: Related Researchmentioning

confidence: 99%

See 1 more Smart Citation

An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions

Münch

Wehn

Glesner

1997

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

Section: Related Researchmentioning

confidence: 99%

“…It relies on a similar methodology as the one suggested in [8], but allows the combination of all three types of timing specifications within a single description. The BFSM model supports more complex timing constraints, however, it cannot directly be incorporated into a VHDL-based design and simulation environment.…”

Section: Related Researchmentioning

confidence: 99%

An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions

Münch

Wehn

Glesner

1997

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…Memory accesses are regarded as Input/Output. The I/O behavior and number of control step are managed in function of the scheduling mode [5]. In practice, the number of nodes in their input specifications must be limited, to obtain a realistic and satisfying architectural solution.…”

Section: Introductionmentioning

confidence: 99%

Memory accesses management during high level synthesis

Corre

Senn

Bomel

et al. 2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

View full text Add to dashboard Cite

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

show abstract

“…Memory accesses are regarded as Input/Output. The I/O behavior and number of control step are managed in function of the scheduling mode [3]. In practice, the number of nodes in their input specifications must be limited, to obtain a realistic and satisfying architectural solution.…”

Section: Introductionmentioning

confidence: 99%

A memory aware behavioral synthesis tool for real-time VLSI circuits

Corre

Senn

Julien

et al. 2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

We introduce a new approach to take into account the memory architecture and the memory mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

show abstract

Behavioral synthesis methodology for HDL-based specification and validation

Cited by 36 publications

References 6 publications

An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions

An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions

Memory accesses management during high level synthesis

A memory aware behavioral synthesis tool for real-time VLSI circuits

Contact Info

Product

Resources

About