Memory accesses management during high level synthesis

Corre, Gwenolé; Senn, Eric; Bomel, Pierre; Julien, Nathalie; Martin, Éric

doi:10.1145/1016720.1016733

Cited by 12 publications

(10 citation statements)

References 8 publications

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“…The mandatory constraints are the throughput (specified through an Initiation Interval II which represents the constant interval between the start of successive iterations) and the clock period. Optional design constraints are memory mapping [9] and 110 timing diagram [10] [11].…”

Section: Gautoverviewmentioning

confidence: 99%

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High-Level Synthesis: On the path to ESL design

Coussy

Heller

2011

2011 9th IEEE International Conference on ASIC

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In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow (a VHDLNerilog RTL specification, followed by logical and physical synthesis) is no more suitable. Designing MPSoC requires new design approaches raising the specification abstraction up to Electronic System Level (ESL). Hence, virtual prototyping, design space exploration and high-level/system synthesis with the goal of optimised and functionally correct product implementation are needed. In this paper, we present the High-Level Synthesis (HLS) tool named GAUT. From a bit-accurate C/C++ specification and a set of design constraints, GAUT automatically generates a potentially pipelined RTL architecture described in both VHDL and SystemC respectively used for synthesis and virtual prototyping. Results demonstrate the interest of the tool on a MJPEG application and its capability in exploring various SoC design tradeoffs including several hardware accelerators HW-ACCs.

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Section: Gautoverviewmentioning

confidence: 99%

“…as needed. It is composed of memory banks and their associated controllers [9] [13]. The COMU allows to interface the HW-ACC with its environment.…”

Section: Gautoverviewmentioning

confidence: 99%

High-Level Synthesis: On the path to ESL design

Coussy

Heller

2011

2011 9th IEEE International Conference on ASIC

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“…This design step relies on the synthesis of different IP core architectural parts: Processing Unit (PU), Memory Unit (MU), Control Unit (CU), Communication Unit (COMU). The MU synthesis does not directly depend on the GCG modelling but is related to the operation scheduling (see for example [5]). The CU generation is a general problem described for instance in [10,9].…”

Section: Ip Hardware Synthesismentioning

confidence: 99%

Constrained algorithmic IP design for system-on-chip

Coussy¹,

Casseau²,

Bomel³

et al. 2007

Integration

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“…A recent study by Stitt et al [16] shows how words recently read from memory can be reused. 3) Access ordering and access scheduling: A huge body of work in HLS systems addresses the problem of static scheduling in memory-intensive applications [5], [6], [17]- [19]. Most of these efforts start with a control dataflow-graph specification, where memory references are explicitly marked (i.e., statically disambiguated).…”

Section: A Specification Supportmentioning

confidence: 99%

Hardware compilation of application-specific memory-access interconnect

Venkataramani

Bjerregaard

Chelcea

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.Index Terms-Communication synthesis, dataflow synthesis, high-level synthesis (HLS), interface design.

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Memory accesses management during high level synthesis

Cited by 12 publications

References 8 publications

High-Level Synthesis: On the path to ESL design

High-Level Synthesis: On the path to ESL design

Constrained algorithmic IP design for system-on-chip

Hardware compilation of application-specific memory-access interconnect

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