Behavioral modeling of WCDMA transceiver with VHDL-AMS language

Joannon, Yves; Beroulle, Vincent; Khouri, R.; Robach, Chantal; Tedjini, Smaïl; Carbonero, J.L.

doi:10.1109/ddecs.2006.1649589

Cited by 7 publications

(6 citation statements)

References 3 publications

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“…The top to bottom methodology is the opposite way to the bottom to top methodology. One of the advantages of this methodology is that behavioral models have previously been built, so each structural block description can be validated in the overall system using other block behavioral models [19] . Moreover, the "meet in the middle" methodology is a method between the top to bottom and bottom to top methodologies.…”

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

“…(1) Injecting only the chosen fault into the low level cell by using a tool such as ANTICS [25] , PLASMA [18] , and then observing the fault effects on the specifications of the models at higher levels of design hierarchy [19,26] . ANTICS and PLAMA are both able to generate different types of faults in a circuit and then perform TLFS.…”

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

“…Models, which can refer to both "circuits" and "devices", are produced by combining lower-level building blocks to create higher-level building blocks. Lower-level blocks can be either elemental models or previously created hierarchical models, elemental intrinsic building blocks are at the bottom of all hierarchical models [19] . Fig.…”

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

“…An electronic system consists of three possible abstraction hierarchies [19] : the bottom to top methodology, the top to bottom methodology and "meet the middle methodology". The top to bottom methodology is the opposite way to the bottom to top methodology.…”

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

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Review of high level fault modeling approaches for mixed-signal systems

Xia

Ian

Antony

2010

J. Electron.(China)

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In the modern analogue design, Transistor Level Fault Simulation (TLFS) plays the important part since every fault in the whole circuit has to be simulated at that level. Unfortunately, it is a very CPU intensive task even though it maintains the high accuracy. Therefore, High Level Fault Modeling (HLFM) and High Level Fault Simulation (HLFS) are required in order to alleviate the efforts of simulation. In this paper, different HLFM approaches are reviewed at the device level during last two decades. We clarify their domains of application and evaluate their strengths and current limitations. We also analyze causes of faults and introduce various test approaches.

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Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

Section: High Level Fault Modeling and Simulationmentioning

confidence: 99%

See 2 more Smart Citations

Review of high level fault modeling approaches for mixed-signal systems

Xia

Ian

Antony

2010

J. Electron.(China)

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“…Digital registers (not illustrated in Figure 1) control the LNA and VGA gains. These registers permit to control the receiver parameters; they can be used to control the system during validation [3]. …”

Section: Wcdma Systemmentioning

confidence: 99%

Choice of a High‐Level Fault Modelfor the Optimization of Validation Test Set Reused for Manufacturing Test

et al. 2008

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Recommended by Bozena KaminskaWith the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

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