Choice of a High‐Level Fault Modelfor the Optimization of Validation Test Set Reused for Manufacturing Test

Abstract

Recommended by Bozena KaminskaWith the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

Review of high level fault modeling approaches for mixed-signal systems

“…However, the gate open is more difficult to model, especially when floating capacitors are produced. One way to approach the problem is to set up voltage in the real device on this capacitor in order to implement simulation, for example [23] sets gate voltage to 0 V. Fault models can be written in either SPICE (e.g., HSPICE [24] ) or Hardware Description Language (HDL) such as VHDL-AMS [17,18] . However, the behavioral model in Ref.…”

“…(1) Injecting only the chosen fault into the low level cell by using a tool such as ANTICS [25] , PLASMA [18] , and then observing the fault effects on the specifications of the models at higher levels of design hierarchy [19,26] . ANTICS and PLAMA are both able to generate different types of faults in a circuit and then perform TLFS.…”

“…(2) High level fault models are obtained by abstracting faults from transistor level into a behavioral description of their effects [18,27,28] . The behavioral models used in Ref.…”

“…The behavioral models used in Ref. [18,28] are simple linear models, so it may not be applicable to strong nonlinear behavior. Moreover, the system does not automatically generate behavioral to perform HLFM such as Ref.…”

“…During the last few years, High Level Fault Modeling (HLFM) and High Level Fault Simulation (HLFS) techniques have been proposed for modern complex analogue and mixed mode system design due to its high speed [16][17][18] . Further details can be found in Section II.…”