BDD based synthesis of Boolean functions using memristors

Chakraborti, Sayak; Chowdhary, P. Varun; Datta, Kamalika; Sengupta, Indranil

doi:10.1109/idt.2014.7038601

Cited by 48 publications

(57 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Sum of the RRAM counts by the proposed multi-objective algorithm is almost 19.78% lower than the same value by the proposed algorithm for step optimization at a cost of 21.09% increase in the sum of the number of steps which confirms the good trad-off and high efficiency in the resulting circuits. Table III shows the comparison of results of the proposed multi-objective MIG optimization algorithm for RRAM-based logic circuits obtained by both proposed realizations with the results by two previous works using BDD-based [11] and AIGbased [12] synthesis. Both works exploit optimization to lower the number of RRAMs and computational steps.…”

Section: B Optimization Resultsmentioning

confidence: 99%

“…Experiments confirm the superiority of MIGs to BDDs and AIGs in RRAM-based circuit design and the effectiveness of the proposed optimization algorithms. According to the results, the circuits represented and optimized by the proposed MIG-based synthesis approach for large benchmark functions are about 26 times faster than the RRAM-based circuits implemented by the BDD-based and AIG-based synthesis approaches presented in [11], [12].…”

Section: Introductionmentioning

confidence: 99%

“…In order to map MIGs to the equivalent RRAM-based circuits, we first present two realizations for majority gate: (i) a realization based on IMP that is also used by previous works using BDDs [11] and AIGs [12], and (ii) a realization that exploits the built-in resistive majority property of RRAMs denoted by MAJ. Then, we propose two MIG optimization algorithms for synthesis of RRAM-based logic circuits: (i) a multi-objective optimization algorithm to reduce the number of required RRAMs and computational steps representing area and delay of the resulting circuits, respectively, and (ii) an optimization algorithm tailored to reduce the number of computational steps as the main concern of RRAM-based logic design.…”

Section: Introductionmentioning

confidence: 99%

“…This enables designing memories with computing capability, however, the number of computational steps is a serious drawback of implication logic [10]. Using data structures such as Binary Decision Diagrams (BDDs) [11] and And-Inverter Graphs (AIGs) [12] has been previously proposed for optimization of RRAM-based circuits. However, both approaches presented in [11], [12] require a high number of computational steps.…”

Section: Introductionmentioning

confidence: 99%

“…Using data structures such as Binary Decision Diagrams (BDDs) [11] and And-Inverter Graphs (AIGs) [12] has been previously proposed for optimization of RRAM-based circuits. However, both approaches presented in [11], [12] require a high number of computational steps.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

Shirinzadeh

Soeken

Gaillardon

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Abstract-Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed MajorityInverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMPbased realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing-particularly in MAJ-based realizations-and the use of techniques proposed for optimization.

show abstract

Section: B Optimization Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

Shirinzadeh

Soeken

Gaillardon

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

High‐performance digital logic implementation approach using novel Memristor‐based multiplexer

Karimi

Rezai

2019

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents and evaluates novel approaches to design efficientMemristor-based multiplexers. Three novel algorithms and structures are proposed based on IMP logic operation. These novel algorithms and structures are developed based on Memristors and crossbar Nano wires. The proposed Memristor-based multiplexers can store the output inside the Memristors. So, the proposed multiplexers have the ability to compute in memory. The proposed multiplexers are simulated using Pspice. The number of required Memristors and necessary steps to accumulate the output for the proposed 2 to 1 multiplexers is reduced in comparison with the former best MUXs. Moreover, these novel multiplexers are utilized to design ISCAS'85 benchmark circuits. The results show improvements in terms of total propagation delay and the required layout area. KEYWORDS crossbar arrays, IMPLY logics, Memristors, Multiplexer, nanoscale logic operation | INTRODUCTIONTwo important factors of electronic devices are speed and density. 1-3 For a long time, Field Effect Transistors (FETs) had the frontier in this field, but due to scaling limitation, new designs and methodologies are required. 1-3 Some of these approaches that help to overcome these limitations are hybrid Nano/CMOS technologies, 1-4 Graphene Nanoribbon Field Effect Transistors (GNFETs), Silicon on Insulator Field Effect Transistors (SOIFETs), and Carbon Nano Tube Field Effect Transistors (CNTFETs). 1-3 The most promising approach is considered to be the new Nano/CMOS technology. 5 The basic element in this technology is Memristor, which is capable of being scaled to Nano metric sizes. 6 It can also be utilized as resistive memories due to its resistive performance. 7 These resistive memory arrays are usually integrated upon a CMOS subsystem. [8][9][10][11][12] The hybrid Nano/CMOS technology has helped to improve three main classes: (a) digital analogue programmable systems, 13-15 (b) nonvolatile memories, 14 and neuromorphic computing structure. [16][17][18] Material Implication (IMP) is one of the most recently used Memristor-based logic. Based on the IMP logic, many different logic gates such as NOR-OR, 19,20 AND-NAND 21,22 and XNOR-XOR 23 with different architectures have been designed. Recently with the help of IMP logic operations, new Memristor-based multiplexers are also designed. [24][25][26][27] These new logic operations especially NAND gates and multiplexers can help to further improve many arithmetic and computational structures. This is due to the fact that both of these logic operands are capable of designing universal logic circuits. 24 A universal logic circuit can perform like all of the logic gates operations. 24 The unique characteristic of IMP logic operations is that they utilize only Memristors in their structures. 21 Therefore, due to the scaling capabilities of Memristors, the logic gate and multiplexer design with this method could be scaled to Nano metric sizes. 23 In addition, Memristor-based logics are proven to be faster, because of the fast response of

show abstract

Synthesis for Logic-in-Memory Computing Using RRAM

Shirinzadeh

Drechsler

2019

In-Memory Computing

View full text Add to dashboard Cite

BDD based synthesis of Boolean functions using memristors

Cited by 48 publications

References 13 publications

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs

High‐performance digital logic implementation approach using novel Memristor‐based multiplexer

Synthesis for Logic-in-Memory Computing Using RRAM

Contact Info

Product

Resources

About