Batch fabrication of nanopatterned graphene devices via nanoimprint lithography

Abstract

Previous attempts to tune the electrical properties of large-scale graphene via nanopatterning have led to serious degradation of the key electrical parameters that make graphene a desirable material for electronic devices. We use thermal nanoimprint lithography to pattern wafer-scale graphene on a 4-in. wafer with prefabricated 25 mm2 devices. The nanopatterning process introduces a modest decrease in carrier mobility and only a minor change in residual doping. Due to the rapid fabrication time of approximately 90 min per wafer, this method has potential for large-scale industrial production. The chemiresistive gas sensing response towards NO2 was assessed in humid synthetic air and dry air, with devices showing a response to 50 ppb of NO2 only when nanopatterned.

Quality assessment of terahertz time-domain spectroscopy transmission and reflection modes for graphene conductivity mapping

“…We attribute the difference between measurements to minor changes in the ambient conditions between the three labs as well as contamination during handling and transferring. Ambient conditions are well known to affect the conductivity of graphene, such as temperature [34] and humidity [35], with each factor known to potentially contribute to a change in conductivity greater than the difference between our measurements. In order to confirm this for our device type, the vdP sheet conductivity was measured at various humidity levels, and between 25 -35 °C as shown in Fig.…”

Lithographic band structure engineering of graphene

“…This has led to more than a decade of research into ways of archiving dense nanostructuring of graphene without compromising the transport properties, but so far disorder at edges increasingly dominate transport measurements as pattern densities increase [22][23][24]. Figure 1 summarise a subset of key experimental works [19,20,[25][26][27][28][29][30][31] featuring twodimensional (2D) nanostructured graphene as well as microscale Hall bars for reference [31], with the reported charge carrier mobility, µ, plotted against the minimum feature size of the system. Here the mobility is calculated from the Drude model of conductivity, σ = neµ, where e is the electron charge.…”

“…Here the mobility is calculated from the Drude model of conductivity, σ = neµ, where e is the electron charge. In early devices fabricated from non-encapsulated graphene, extremely small and dense features have indeed been achieved with block copolymer (BCP) [25] masks, electron-beam lithography (EBL) [26,29,30], nanosphere lithography (NSL) [28], and nano-imprint lithography (NIL) [27]. However, the resulting charge carrier mobilities and associated mean free paths in these works were too low to support quantum transport of the charge carriers beyond semiclassical transport.…”

“…Curabitur consectetuer. EBL BCP [25] EBL [26] NIL [27] NSL [28] EBL [29] EBL [19] EBL [20] EBL [31] EBL [30] This work Minimum feature size, w (nm)…”

Atomic Layer Deposition Alumina‐Mediated Graphene Transfer for Reduced Process Contamination

“…Gated electrical devices were fabricated by transferring graphene onto 300 nm SiO 2 /Si chips with preevaporated Cr/Au contacts using the transfer method stated previously. After a thermal treatment of 225 °C for 30 min in N 2 , the two‐point resistance ( R ) of devices was measured as a function of gate bias ( V G ) at room temperature in a N 2 environment, as previously described …”