Balancing soft error coverage with lifetime reliability in redundantly multithreaded processors

Siddiqua, Taniya; Gurumurthi, Sudhanva

doi:10.1109/mascot.2009.5363142

Cited by 8 publications

(9 citation statements)

References 36 publications

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“…In the P6 style pipeline on which we have performed our experiments, the ROB also plays the role of the physical register file. Though our technique does not help to mitigate the vulnerability of the execution units, the soft error vulnerability of execution units has been observed to be small (around 9%) [2] compared to other micro-architectural structures like ROB, LSQ and ISQ [11], where instructions tend to spend most of their lifetime. Instructions present in these structures are checkpointed periodically depending on the AVF of the system.…”

Section: Introductionmentioning

confidence: 80%

Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM

Swaminathan

Mukundrajan

Soundararajan

et al. 2011

2011 IEEE Computer Society Annual Symposium on VLSI

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Transistor scaling and reduction in operating voltages have resulted in cosmic-ray induced soft errors becoming a major threat for reliable processor operation. With the raw device soft error rate expected to remain constant in future generations, the explosion in on-chip transistor count is expected to have a corresponding impact on overall error rate. Consequently it becomes necessary to incorporate resiliency into the pipeline datapath. However, existing methods like redundant execution or error correction used in memory are non-ideal for the pipeline due to their impact on overall performance.In this paper, we propose a novel technique that exploits the characteristics of Spin Transfer Torque -Magnetic Random Access Memory (STT-MRAM) for providing protection of all storage structures in the pipeline, namely the Reorder Buffer, Issue Queue and Load-Store Queue. We identify specific periods during an application's runtime when the MRAM can capture a "snapshot" of the invariant micro-architectural state and restore it later thereby reducing soft error vulnerability. We quantify the reduction in Architectural Vulnerability Factor (AVF) to be 32% on average, with a performance overhead of less than 6%. Further, we present a case where the proposed technique can be combined with existing soft error protection techniques like Instruction Duplication to further enhance system reliability.

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Section: Introductionmentioning

confidence: 80%

Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM

Swaminathan

Mukundrajan

Soundararajan

et al. 2011

2011 IEEE Computer Society Annual Symposium on VLSI

View full text Add to dashboard Cite

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“…Although we consider both integer and floating-point benchmarks in our evaluations, several of the floating-point benchmarks have a considerable number of integer instructions in their instruction mix and therefore make heavy use of the the integer ALUs [14]. We present our results for only the integer ALU with the lowest sequence number since this ALU tends to be the most heavily utilized of all the ALUs with conventional instruction scheduling, as explained in Section 3.2.…”

Section: Methodsmentioning

confidence: 99%

“…For example, the higher the number of integer instructions, the higher is the probability of accessing integer FUs. A previous study by Siddiqua et al [14] gives the breakdown of the instruction mix of these benchmarks. We find that the lowest guardband reductions are observed for those benchmarks which have a high percentage of integer instructions.…”

Section: Circuit-level Optimizationmentioning

confidence: 99%

A multi-level approach to reduce the impact of NBTI on processor functional units

Siddiqua

Gurumurthi

2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture levels. In this paper, we propose a multi-level optimization approach, combining techniques at the circuit and microarchitecture levels, for reducing the impact of NBTI on the functional units (FUs) of a highperformance processor core. We perform SPICE simulations to evaluate the impact of circuit-level design optimizations to reduce the NBTI guardband in terms of area, delay, and power. We then propose a set of NBTI-aware dynamic instruction scheduling policies at the microarchitecture level and quantify their impact on application performance and guardband reduction through executiondriven simulation. We show that carefully combining techniques at both these levels provides the most attractive solution to reducing the guardband while imposing the least overhead in terms of area, power, delay, and application performance.

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“…Although we consider both integer and floating-point benchmarks in our evaluations, several of the floatingpoint benchmarks have a considerable number of integer instructions in their instruction mix and therefore make heavy use of the the integer ALUs [45]. We present our results for only the integer ALU with the lowest sequence number since this ALU tends to be the most heavily utilized of all the ALUs with conventional instruction scheduling, as explained in Section 5.1.2.…”

Section: Methodsmentioning

confidence: 99%

“…A previous study by Siddiqua et al [45] gives the breakdown of the instruction mix of these benchmarks. We find that the lowest guardband reductions are observed for those benchmarks which have a high percentage of integer instructions.…”

Section: Circuit-level Optimizationmentioning

confidence: 99%

A Multi-Level Approach to NBTI Mitigation in Processors

Siddiqua

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We are in the era of multicore processors and it is expected that the number of the processing cores on a chip will steadily increase over the next decade, driven by Moore's Law. While technology scaling has benefitted high performance, the scaling has a dark side too: a degradation in the reliability of silicon devices. Processors have become highly susceptible to a variety of reliability problems in silicon, such as particle induced soft errors and hard errors. Therefore, processors have to be designed to provide adequate protection against these reliability problems while maintaining high performance and energy efficiency. Designing a reliable computer system is a large and complex multi-dimensional and multi-level problem, comprising of different hardware blocks, reliability phenomena, design layers, metrics, and optimization techniques. This dissertation considers a key emerging reliability phenomenon: Negative Bias Temperature Instability (NBTI). This dissertation develops NBTI mitigation techniques for the logic and memory structures in the processor that impose very little performance, power, and area overheads. This research also creates the foundation for understanding NBTI in the context of one other important processor reliability problem: process variations.

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Balancing soft error coverage with lifetime reliability in redundantly multithreaded processors

Cited by 8 publications

References 36 publications

Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM

Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM

A multi-level approach to reduce the impact of NBTI on processor functional units

A Multi-Level Approach to NBTI Mitigation in Processors

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