The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device-the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.
Transistor scaling and reduction in operating voltages have resulted in cosmic-ray induced soft errors becoming a major threat for reliable processor operation. With the raw device soft error rate expected to remain constant in future generations, the explosion in on-chip transistor count is expected to have a corresponding impact on overall error rate. Consequently it becomes necessary to incorporate resiliency into the pipeline datapath. However, existing methods like redundant execution or error correction used in memory are non-ideal for the pipeline due to their impact on overall performance.In this paper, we propose a novel technique that exploits the characteristics of Spin Transfer Torque -Magnetic Random Access Memory (STT-MRAM) for providing protection of all storage structures in the pipeline, namely the Reorder Buffer, Issue Queue and Load-Store Queue. We identify specific periods during an application's runtime when the MRAM can capture a "snapshot" of the invariant micro-architectural state and restore it later thereby reducing soft error vulnerability. We quantify the reduction in Architectural Vulnerability Factor (AVF) to be 32% on average, with a performance overhead of less than 6%. Further, we present a case where the proposed technique can be combined with existing soft error protection techniques like Instruction Duplication to further enhance system reliability.
Energy efficiency is considered to be the most critical design parameter for ubiquitous and mobile computing systems. With consumers expecting improved functionality and performance from these systems without compromising on battery life, there is urgent need to explore emerging technologies that can overcome the limitations of CMOS and deliver greater energy efficiency. The potential of one such prospective metal oxide semiconductor field effect transistor replacement device, the tunnel FET (TFET), is evaluated in this study. Novel circuit designs are presented to overcome unique design challenges posed by TFETs. Further, the impact of TFETs at different levels of design abstraction is characterised by evaluating a novel sparse prefix tree adder and a field programmable gate array. A considerable improvement in delay and significant reduction in energy is observed because of the combined impact of circuit and technology co-exploration.
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