Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators

2021

Preprint

Recent advances in reprogrammable hardware (e. g., FPGAs) and memory technology (e. g., DDR4, HBM) promise to solve performance problems inherent to graph processing like irregular memory access patterns on traditional hardware (e. g., CPU). While several of these graph accelerators were proposed in recent years, it remains difficult to assess their performance and compare them on common graph workloads and accelerator platforms, due to few open source implementations and excessive implementation effort.In this work, we build on a simulation environment for graph processing accelerators, to make several existing accelerator approaches comparable. This allows us to study relevant performance dimensions such as partitioning schemes and memory technology, among others. The evaluation yields insights into the strengths and weaknesses of current graph processing accelerators along these dimensions, and features a novel in-depth comparison.

Section: Related Workmentioning

confidence: 99%

Demystifying Memory Access Patterns of FPGA-Based Graph Processing Accelerators

Dann¹,

Ritter²,

2021

Preprint

“…Upon level synchronization, active vertices are exchanged between the PEs. A memory access improvement for vertex-centric graph processing is given by Yan et al [137]. Random memory accesses are sequenced and graph pruning is applied to prevent ongoing traversal from the leaves.…”

Section: Compressed Sparse Row (Csr)mentioning

confidence: 99%

“…Other [15,92,137] Bloom filter [30]; Flash [19,136] Performance Horizontal partitioning In [148] a horizontal partitioning scheme is proposed with an improved data layout enabling more sequential write accesses. This is achieved by sorting the edges in each partition by destination vertex which also allows update merging.…”

Section: Memory Accessmentioning

confidence: 99%

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Non-Relational Databases on FPGAs: Survey, Design Decisions, Challenges

Dann¹,

Ritter²,

2020

Preprint

Non-relational database systems (NRDS), such as graph, document, key-value, and wide-column, have gained much attention in various trending (business) application domains like smart logistics, social network analysis, and medical applications, due to their data model variety and scalability. The broad data variety and sheer size of datasets pose unique challenges for the system design and runtime (incl. power consumption). While CPU performance scaling becomes increasingly more difficult, we argue that NRDS can benefit from adding field programmable gate arrays (FPGAs) as accelerators. However, FPGA-accelerated NRDS have not been systematically studied, yet.To facilitate understanding of this emerging domain, we explore the fit of FPGA acceleration for NRDS with a focus on data model variety. We define the term NRDS class as a group of non-relational database systems supporting the same data model. This survey describes and categorizes the inherent differences and nontrivial trade-offs of relevant NRDS classes as well as their commonalities in the context of common design decisions when building such a system with FPGAs. For example, we found in the literature that for keyvalue stores the FPGA should be placed into the system as a smart network interface card (SmartNIC) to benefit from direct access of the FPGA to the network. However, more complex data models and processing of other classes (e. g., graph and document) commonly require more elaborate near-data or socket accelerator placements where the FPGA respectively has the only

“…However, they do not show performance numbers generated with this simulation. [Ya19] uses Ramulator as the underlying DRAM simulator for a custom cycleaccurate simulation of the accelerator Graphicionado [Ha16]. However, this incurs very high implementation time.…”

Section: Related Workmentioning

confidence: 99%

Exploring Memory Access Patterns for Graph Processing Accelerators

Dann¹,

Ritter²,

2020

Preprint

Recent trends in business and technology (e. g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph processing with a customizable memory hierarchy promise solving performance problems caused by inherent irregular memory access patterns on traditional hardware (e. g., CPU). However, developing such hardware accelerators is yet timeconsuming and difficult and benchmarking is non-standardized, hindering comprehension of the impact of memory access pattern changes and systematic engineering of graph processing accelerators.In this work, we propose a simulation environment for the analysis of graph processing accelerators based on simulating their memory access patterns. Further, we evaluate our approach on two state-ofthe-art FPGA graph processing accelerators and show reproducibility, comparablity, as well as the shortened development process by an example. Not implementing the cycle-accurate internal data flow on accelerator hardware like FPGAs significantly reduces the implementation time, increases the benchmark parameter transparency, and allows comparison of graph processing approaches.