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Non-relational database systems (NRDS), such as graph, document, key-value, and wide-column, have gained much attention in various trending (business) application domains like smart logistics, social network analysis, and medical applications, due to their data model variety and scalability. The broad data variety and sheer size of datasets pose unique challenges for the system design and runtime (incl. power consumption). While CPU performance scaling becomes increasingly more difficult, we argue that NRDS can benefit from adding field programmable gate arrays (FPGAs) as accelerators. However, FPGA-accelerated NRDS have not been systematically studied, yet.To facilitate understanding of this emerging domain, we explore the fit of FPGA acceleration for NRDS with a focus on data model variety. We define the term NRDS class as a group of non-relational database systems supporting the same data model. This survey describes and categorizes the inherent differences and nontrivial trade-offs of relevant NRDS classes as well as their commonalities in the context of common design decisions when building such a system with FPGAs. For example, we found in the literature that for keyvalue stores the FPGA should be placed into the system as a smart network interface card (SmartNIC) to benefit from direct access of the FPGA to the network. However, more complex data models and processing of other classes (e. g., graph and document) commonly require more elaborate near-data or socket accelerator placements where the FPGA respectively has the only

Non-relational database systems (NRDS) such as graph and key-value have gained attention in various trending business and analytical application domains. However, while CPU performance scaling becomes increasingly more difficult, FPGA-accelerated NRDS have not been systematically studied, yet. This survey describes and categorizes the inherent differences and non-trivial trade-offs of relevant NRDS classes (i. e., graph, document, key-value, and wide-column) as well as their commonalities in the context of common design decisions when building such a system with FPGAs. In particular, we highlight accelerator tasks, FPGA placement, accelerator design patterns, and justification for using FPGAs in different system contexts. We close with open research and engineering challenges to outline the future of FPGA-accelerated NRDS.