Backside laser testing of ICs for SET sensitivity evaluation

Lewis, Dean; Pouget, Vincent; Beaudoin, Félix; Perdu, Philippe; Lapuyade, Hervé; Fouillat, P.; Touboul, A.

doi:10.1109/23.983195

Cited by 73 publications

(24 citation statements)

References 13 publications

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“…Another interesting point is the hint of the presence of buried highly doped layers [9]. According to the literature, bipolar transistors in the differential pair found in the input stage core are very sensitive to charge deposition.…”

Section: Discussionmentioning

confidence: 99%

Two-Photon Absorption (TPA) backside pulsed laser tests in the LM324

Lopez-Calle

Franco

Izquierdo

et al. 2009

2009 European Conference on Radiation and Its Effects on Components and Systems

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Section: Discussionmentioning

confidence: 99%

Two-Photon Absorption (TPA) backside pulsed laser tests in the LM324

Lopez-Calle

Franco

Izquierdo

et al. 2009

2009 European Conference on Radiation and Its Effects on Components and Systems

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“…In lieu of heavy ion testing, pulsed laser irradiation has grown as an evaluation technique, largely due to the work of several groups [37,38,[51][52][53]. While there have been several direct comparisons of pulsed laser data to heavy ion data, cf.…”

Section: Discussion and Summarymentioning

confidence: 99%

“…4. Two-photon absorption [37,38] is ideally suited for testing SDRAMs since it injects photons through the backside of the die and most SDRAMs are flip-chip mounted -shown in Fig. 4(a).…”

Section: Evaluating Spacecraft Memory Technologiesmentioning

confidence: 99%

Practicality of evaluating soft errors in commercial sub-90 nm CMOS for space applications

Pellish

LaBel

2010

2010 IEEE International Reliability Physics Symposium

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Abstract-Inclusion of commercial technologies in civil spaceflight applications is reality. These technologies enable higher performance, reduce power consumption, and ultimately yield better science. However, the benefits do not come without cost, and radiation-induced soft errors in advanced, sub-90 nm CMOS technologies present new challenges. These challenges include sensitivity to proton direct ionization, memory technology evaluation, as well as testing and evaluation complexity.

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“…Laser injection from the interconnect side and from the Si backside have been widely reported in the literature [8,9]. In this work backside laser exposure is used because the interconnect layers present in Intel's 22nm/32nm technology nodes [10] are very dense.…”

Section: B Laser Datamentioning

confidence: 99%