Avalanche Photodiodes in Submicron CMOS Technologies for High-Sensitivity Imaging

Betta, Gian-Franco Dalla; Pancheri, Lucio; Stoppa, David; Henderson, Robert K.; Richardson, Julia M.

doi:10.5772/15178

Cited by 28 publications

(5 citation statements)

References 57 publications

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“…Using coincidence between vertically aligned SPAD cell pairs is a key aspect because it can dramatically reduce the dark count rate. This is particularly important since, in order to reduce the system complexity and the power consumption, the electronics should be monolithically integrated with SPADs in a CMOS technology, for which it is not easy to obtain SPADs with low dark count figures [26]. In terms of efficiency, encouraging results have been obtained from tests with SiPMs having an active thickness of a few µm [27], but they should be confirmed with CMOS SPADs where the active thickness is even smaller (∼1 µm).…”

Section: Jinst 10 C07010 2 Recent Advances In Planar Pixel Sensorsmentioning

confidence: 99%

Why and how pixels are becoming more and more “intelligent” (sensors—part 2)

Betta¹

2015

J. Inst.

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Although most of the pixel “intelligence” is normally found on the electronics side, some important progress has been recently achieved in radiation sensors themselves, allowing for significant performance improvement and new application opportunities. This paper is focused on the most interesting elements of novelty that have characterized pixel sensors in the past few years, with emphasis on device and technological aspects. In particular, sensors exploiting the third dimension in silicon (i.e., 3D sensors and active edge sensors) are reviewed in detail.

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Section: Jinst 10 C07010 2 Recent Advances In Planar Pixel Sensorsmentioning

confidence: 99%

Why and how pixels are becoming more and more “intelligent” (sensors—part 2)

Betta¹

2015

J. Inst.

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“…A p-n junction consisting for example of a n+ diffusion over a p-type substrate cannot be suitable for an avalanche diode because of the curvature at the device edge leading to a local higher electric field and thus causing premature edge breakdown (PEB). In this preliminary work, some PEB prevention techniques found in literature [3][4][5] have been studied by TCAD simulations [6] adopting 2D Cylindrical models and 130nm CMOS process technological data. Simulations results are briefly discussed in the following subsections.…”

Section: Apix Implementation In Standard Cmos Technologymentioning

confidence: 99%

“…Thanks to a low doped p-well surrounding the p+ diffusion the electric field can be successfully smoothed down [3] (figure 1). However this layout may violate the design rules of a standard CMOS process as the intersection of diffusion and well regions, e.g.…”

Section: Low Doped Guard Ringmentioning

confidence: 99%

Preliminary simulation study of a coincidence Avalanche Pixel Sensor

Vignetti¹,

Calmon²,

Cellier³

et al. 2015

J. Inst.

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“…HE performance of CMOS image sensors based on Single Photon Avalanche Diodes (SPADs) has been tremendously improved in the last years [1], [2]. They have been proven for photon counting and Time-of-Flight (ToF) [3].…”

Section: Introductionmentioning

confidence: 99%

Compact Real-Time Inter-Frame Histogram Builder for 15-Bits High-Speed ToF-Imagers Based on Single-Photon Detection

et al. 2019

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Time-of-flight image sensors based on single-photon detection, i.e. SPADs, require some filtering of pixel readings. Accurate depth measurements are only possible if the jitter of the detector is mitigated. Moreover, the time stamp needs to be effectively separated from uncorrelated noise such as dark counts and background illumination. A powerful tool for this is building a histogram of a number of pixel readings. Future generation of ToF imagers are seeking to increase spatial and temporal resolution along with the dynamic range and frame rate. Under these circumstances, storing the complete histogram for every pixel becomes practically impossible. Considering that most of the information contained by the histogram represents noise, we propose a highly efficient method to store just the relevant data required for ToF computation. This method makes use of the shifted inter-frame histogram (SifH). It requires a memory as low as 128 times smaller than storing the complete histogram if the pixel values are coded on up to 15 bits. Moreover, a fixed 2 8 words memory is enough to process histograms containing up to 2 15 bins. In exchange, the overall frame rate only decreases to one half. The hardware implementation of this algorithm is presented. Its remarkable robustness for a low SNR of the ToF estimation is demonstrated by Matlab simulations and FPGA implementation using input data from a SPAD camera prototype. Index Terms-shifted inter-frame histogram (SifH), real-time time-of-flight (ToF) estimation, ToF image sensor, single-photon avalanche-diode (SPAD)

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Avalanche Photodiodes in Submicron CMOS Technologies for High-Sensitivity Imaging

Cited by 28 publications

References 57 publications

Why and how pixels are becoming more and more “intelligent” (sensors—part 2)

Why and how pixels are becoming more and more “intelligent” (sensors—part 2)

Preliminary simulation study of a coincidence Avalanche Pixel Sensor

Compact Real-Time Inter-Frame Histogram Builder for 15-Bits High-Speed ToF-Imagers Based on Single-Photon Detection

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