AutoPilot: A Platform-Based ESL Synthesis System

Zhang, Zhiru; Fan, Yiping; Jiang, Wei; Han, Guoling; Yang, Changqi; Cong, Jason

doi:10.1007/978-1-4020-8588-8_6

Cited by 94 publications

(66 citation statements)

References 5 publications

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“…Its flow includes source-to-source compilation from FCUDA annotated CUDA code to C program for Autopilot. Autopilot is a high-level synthesis tool that converts input specifications in C, C++ or SystemC into RTL descriptions for the target FPGA device [17]. The sourceto-source translator coarsens the granularity and extracts parallelism at the level of thread blocks.…”

Section: Related Workmentioning

confidence: 99%

Enabling development of OpenCL applications on FPGA platforms

Shagrithaya

Kȩpa

Athanas

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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FPGAs can potentially deliver tremendous acceleration in high-performance server and embedded computing applications. Whether used to augment a processor or as a stand-alone device, these reconfigurable architectures are being deployed in a large number of implementations owing to the massive amounts of parallelism offered. At the same time, a significant challenge encountered in their wide-spread acceptance is the laborious efforts required in programming these devices. The increased development time, level of experience needed by the developers, lower turns per day and difficulty involved in faster iterations over designs affect the time-to-market for many solutions. High-level synthesis aims towards increasing the productivity of FPGAs and bringing them within the reach software developers and domain experts. OpenCL is a specification introduced for parallel programming purposes across platforms. Applications written in OpenCL consist of two parts -a host program for initialization and management, and kernels that define the compute intensive tasks. In this thesis, a compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to obtain the design specification for compute cores. An architecture provided integrates the cores with memory and host interfaces. The host program in the application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end. The environment in the lab has always been conducive to learning things the enjoyable way.I would like to thank my lab mates; Tony, for his advice on all work-related matters; Karl, for helping me ramp up in the intial days; Krzysztof, for his help and guidance on this project;Kaiwen, for his inputs towards this work; and the rest of the CCM family, David, Ritesh, Ramakrishna, Keyrun, Xin Xin, Wen Wei, Andrew, Richard, Shaver, Jason, Ryan, Teresa, Abhay and Jacob for making this a truly enriching experience.My heartfelt thanks to Kaushik and Abhinav for their support in curricular and noncurricular aspects; Iccha, Vishwas, Vikas, Shivkumar, Navish, Atashi and Mahesh for the fun times off work; and all my other friends at Blacksburg who have made these two years very memorable for me.

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Section: Related Workmentioning

confidence: 99%

Enabling development of OpenCL applications on FPGA platforms

Shagrithaya

Kȩpa

Athanas

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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“…Finally, the HLS engine synthesizes the generated output code of the SST engine to RTL. In the ML-GPS framework we use a commercial HLS tool [2], which generates highly-optimized RTL code.…”

Section: Sl-gpsmentioning

confidence: 99%

“…As was discussed earlier, Period is affected by all the design space dimensions and is estimated through our estimation model in (2). On the other hand, Cyc is generated by the HLS engine and is only affected by the TH and AP dimensions (i.e.…”

Section: B Design Space Search Algorithm 1) Latency Estimationmentioning

confidence: 99%

“…Ongoing developments in the field of high-level synthesis (HLS) have led to the emergence of several industry [1][2][3] and academia powered [4,5] tools that can generate device-specific RTL descriptions from popular High-Level programming Languages (HLLs). Such tools help raise the abstraction of the programming model and constitute a significant improvement in FPGAs' usability.…”

Section: Introductionmentioning

confidence: 99%

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Multilevel Granularity Parallelism Synthesis on FPGAs

Papakonstantinou

Liang

Stratton

et al. 2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Recent progress in High-Level Synthesis (HLS) techniques has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-generated RTL, involves lengthy logic synthesis and physical design flows. Moreover, mapping of different levels of coarse grained parallelism onto hardware spatial parallelism affects the final FPGA-based performance both in terms of cycles and frequency. Evaluation of the rich design space through the full implementation flow -starting with high level source code and ending with routed netlist -is prohibitive in various scientific and computing domains, thus hindering the adoption of reconfigurable computing. This work presents a framework for multilevel granularity parallelism exploration with HLS-order of efficiency. Our framework considers different granularities of parallelism for mapping CUDA kernels onto high performance FPGA-based accelerators. We leverage resource and clock period models to estimate the impact of multi-granularity parallelism extraction on execution cycles and frequency. The proposed Multilevel Granularity Parallelism Synthesis (ML-GPS) framework employs an efficient design space search heuristic in tandem with the estimation models as well as design layout information to derive a performance near-optimal configuration. Our experimental results demonstrate that ML-GPS can efficiently identify and generate CUDA kernel configurations that can significantly outperform previous related tools whereas it can offer competitive performance compared to software kernel execution on GPUs at a fraction of the energy cost.

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“…The primary goal of C-to-silicon synthesis frameworks such as AutoESL [23], Impulse C [7], Synopsys Synphony/PICO [15], CHiMPS [14], and Altera C2H [11] is to reduce the effort that creating accelerators requires, by building them directly from a high-level language. To accelerate execution, these tools must either infer parallel execution from serial code or force the programmer to rewrite their code in a more explicitly parallel language or dialect [18].…”

Section: Icer Performance and Efficiencymentioning

confidence: 99%

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

Arora

Sampson

Goulding-Hotta

et al. 2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide range of unmodified C programs. FPGAs are increasingly used to build large-scale systems, and many large software systems contain relatively little code that is amenable to automatic, semi-automatic, or even manual parallelization. Whereas accelerator approaches have traditionally achieved energy benefits as a side effect from increasing performance via parallel execution, ICERs aim to achieve energy gains even on code with little exploitable parallelism.Traditional approaches to automatically generating accelerators from existing software rely on inferring parallel execution from serial code, so they face the same code analysis challenges as parallelizing compilers. In contrast, because the ICER approach targets energy rather than performance, it easily scales to large, irregular applications that are poor candidates for traditional acceleration. Our results show that, compared to a baseline system with soft processor cores, ICERs can reduce energy consumption by up to 9.5× for the code they target and 2.8× for whole applications.

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AutoPilot: A Platform-Based ESL Synthesis System

Cited by 94 publications

References 5 publications

Enabling development of OpenCL applications on FPGA platforms

Enabling development of OpenCL applications on FPGA platforms

Multilevel Granularity Parallelism Synthesis on FPGAs

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems

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