Multilevel Granularity Parallelism Synthesis on FPGAs

Papakonstantinou, Alexandros; Liang, Yun; Stratton, John A.; Gururaj, Karthik; Chen, Deming; Hwu, Wen-mei W.; Cong, Jason

doi:10.1109/fccm.2011.29

Cited by 42 publications

(12 citation statements)

References 14 publications

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“…FCUDA [3] is a source-to-source compiler from NVidia's CUDA language to synthesizable AutoPilot C. Building on FCUDA, a highlevel parameter space exploration tool is presented in [6]. The tool first builds a resource and clock-period estimation models by actually synthesizing a small number of sample configurations.…”

Section: Related Workmentioning

confidence: 99%

Reducing Instruction Issue Overheads in Application-Specific Vector Processors

Sýkora

Bartosiński

Kohout

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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The traditional approach to IP core design is to use simulations with test vectors. This is not feasible when dealing with complex function cores such as the Image Segmentation case-study algorithm in this paper. An algorithm developer needs to carry out experiments on large real-world data sets, with fast turn-around times, and in real time to facilitate performance tuning and incremental development. Previously we proposed a methodology called Application-Specific Vector Processor (ASVP). The ASVP approach first constructs a programmable architecture customized for a given application, then employs software techniques to develop firmware that implements the algorithm.In our setting we employ an embedded simple scalar CPU (8-bit PicoBlaze 3) to control a floating-point vector processing unit (VPU) by issuing wide (horizontally encoded) instructions to it. In this work we dramatically reduce the overhead of the wide-instruction issue (in one case by 13x) by implementing a new two-level configuration table. The table stores frequently used vector definitions (in Level 1) and vector instructions (in Level 2), pre-loading them quickly into the issue buffer. A configuration in the issue buffer can be further modified before being sent to the processing unit. This ensures the architecture stays general and fully customizable.

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Section: Related Workmentioning

confidence: 99%

Reducing Instruction Issue Overheads in Application-Specific Vector Processors

Sýkora

Bartosiński

Kohout

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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“…Thus an interesting study would try to find the best of both worlds: take massively parallel applications implemented in massively parallel programming languages and figure out how to map them to ASICs or FPGAs. FCUDA [40], [41], [71], [72], [73], [74] is one such study. The FCUDA compilation process is illustrated in Fig.…”

Section: Fcudamentioning

confidence: 99%

High-level Synthesis for Low-power Design

Zhang

Chen

Dai

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been increasingly difficult, if not already unsustainable. Complexity scaling dictates that this process must be automated with robust analysis and synthesis algorithms at a higher level of abstraction. Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. By allowing early access to the system architecture, high-level decisions during HLS can have a significant impact on the power and energy efficiency of the synthesized design. In this paper, we will discuss the recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations. We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. We will also describe the key power optimization challenges facing HLS today and outline potential opportunities in tackling these challenges.

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“…This work proposes efficient design space exploration techniques for applications that consist of multiple nested loops with or without dataflow dependence. In addition, instead of searching all possible configurations [2][3] [14][20], we prune the design space by eliminating the dominated configurations. Accurate performance and area models are also developed to assist the design space exploration to reduce number of invocation of the HLS tool.…”

Section: Related Workmentioning

confidence: 99%

Design space exploration of multiple loops on FPGAs using high level synthesis

Zhong

Venkataramani

Liang

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-Real-world applications such as image processing, signal processing, and others often contain a sequence of computation intensive kernels, each represented in the form of a nested loop. High-level synthesis (HLS) enables efficient hardware implementation of these loops using high-level programming languages. HLS tools also allow the designers to evaluate design choices with different trade-offs through pragmas/directives. Prior design space exploration techniques for HLS primarily focus on either single nested loop or multiple loops without consideration to the data dependencies among them. In this paper, we propose efficient design space exploration techniques for applications that consist of multiple nested loops with or without data dependencies. In particular, we develop an algorithm to derive the Paretooptimal curve (performance versus area) of the application when mapped onto FPGAs using HLS. Our algorithm is efficient as it effectively prunes the dominated points in the design space. We also develop accurate performance and area models to assist the design space exploration process. Experiments on various scientific kernels and real-world applications demonstrate that our design space exploration technique is accurate and efficient.

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Multilevel Granularity Parallelism Synthesis on FPGAs

Cited by 42 publications

References 14 publications

Reducing Instruction Issue Overheads in Application-Specific Vector Processors

Reducing Instruction Issue Overheads in Application-Specific Vector Processors

High-level Synthesis for Low-power Design

Design space exploration of multiple loops on FPGAs using high level synthesis

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