Enabling development of OpenCL applications on FPGA platforms

Abstract

FPGAs can potentially deliver tremendous acceleration in high-performance server and embedded computing applications. Whether used to augment a processor or as a stand-alone device, these reconfigurable architectures are being deployed in a large number of implementations owing to the massive amounts of parallelism offered. At the same time, a significant challenge encountered in their wide-spread acceptance is the laborious efforts required in programming these devices. The increased development time, level of experience needed by the developers, lower turns per day and difficulty involved in faster iterations over designs affect the time-to-market for many solutions. High-level synthesis aims towards increasing the productivity of FPGAs and bringing them within the reach software developers and domain experts. OpenCL is a specification introduced for parallel programming purposes across platforms. Applications written in OpenCL consist of two parts -a host program for initialization and management, and kernels that define the compute intensive tasks. In this thesis, a compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is presented. The flow uses Xilinx AutoESL tool to obtain the design specification for compute cores. An architecture provided integrates the cores with memory and host interfaces. The host program in the application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end. The environment in the lab has always been conducive to learning things the enjoyable way.I would like to thank my lab mates; Tony, for his advice on all work-related matters; Karl, for helping me ramp up in the intial days; Krzysztof, for his help and guidance on this project;Kaiwen, for his inputs towards this work; and the rest of the CCM family, David, Ritesh, Ramakrishna, Keyrun, Xin Xin, Wen Wei, Andrew, Richard, Shaver, Jason, Ryan, Teresa, Abhay and Jacob for making this a truly enriching experience.My heartfelt thanks to Kaushik and Abhinav for their support in curricular and noncurricular aspects; Iccha, Vishwas, Vikas, Shivkumar, Navish, Atashi and Mahesh for the fun times off work; and all my other friends at Blacksburg who have made these two years very memorable for me.

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

“…Moreover, not all algorithms are amenable to be implemented in a dataflow fashion without loss of generality or efficiency, and the fine-grain acceleration is typically not possible due to the overhead of message-passing communication. Recent research on loosely-coupled accelerators has concentrated on targeting FPGA devices, often trying to hide the underthe-hood model from the developer by exposing a high-level programming model such as OpenCL [41].…”

An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor

“…Prior to the very recent announcement for OpenCL support from Xilinx in the Vivado design suite 2014.2, research was undertaken to convert kernels into AutoESL C code and subsequently, synthesise them to silicon [29]. The Clang AST libraries were used alongside Graphtool to transform these kernels for processing by the synthesis tool; this involved converting barrier calls to barrier_hit and barrier_done signals as well creating interfaces to the block RAMs for the kernel arguments.…”

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

“…Both Altera [16] and Xilinx [17] provide tools to implement OpenCL-compliant applications in their hardware platforms. Hence, researchers from academia have also put their effort in working with OpenCL in order to generate custom accelerators, with tools such as SOpenCL [18], methodologies based upon commercial tools [19] or by using LLVM to accelerate synthesis processes [20].…”